bnx2x.h (fc915c8b930c3114f2a838f7e2cd8789ad6fedc3) bnx2x.h (2e499d3cc13365a87815266dda59904dcb8c8d6c)
1/* bnx2x.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2012 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *

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18#include <linux/types.h>
19
20/* compilation time flags */
21
22/* define this to make the driver freeze on error to allow getting debug info
23 * (you will need to reboot afterwards) */
24/* #define BNX2X_STOP_ON_ERROR */
25
1/* bnx2x.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2012 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *

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18#include <linux/types.h>
19
20/* compilation time flags */
21
22/* define this to make the driver freeze on error to allow getting debug info
23 * (you will need to reboot afterwards) */
24/* #define BNX2X_STOP_ON_ERROR */
25
26#define DRV_MODULE_VERSION "1.72.50-0"
27#define DRV_MODULE_RELDATE "2012/04/23"
26#define DRV_MODULE_VERSION "1.72.51-0"
27#define DRV_MODULE_RELDATE "2012/06/18"
28#define BNX2X_BC_VER 0x040200
29
30#if defined(CONFIG_DCB)
31#define BCM_DCBNL
32#endif
33
34
35#include "bnx2x_hsi.h"

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46#define BNX2X_MIN_MSIX_VEC_CNT 2
47#define BNX2X_MSIX_VEC_FP_START 1
48#endif
49
50#include <linux/mdio.h>
51
52#include "bnx2x_reg.h"
53#include "bnx2x_fw_defs.h"
28#define BNX2X_BC_VER 0x040200
29
30#if defined(CONFIG_DCB)
31#define BCM_DCBNL
32#endif
33
34
35#include "bnx2x_hsi.h"

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46#define BNX2X_MIN_MSIX_VEC_CNT 2
47#define BNX2X_MSIX_VEC_FP_START 1
48#endif
49
50#include <linux/mdio.h>
51
52#include "bnx2x_reg.h"
53#include "bnx2x_fw_defs.h"
54#include "bnx2x_mfw_req.h"
54#include "bnx2x_hsi.h"
55#include "bnx2x_link.h"
56#include "bnx2x_sp.h"
57#include "bnx2x_dcb.h"
58#include "bnx2x_stats.h"
59
60/* error/debug prints */
61

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243 *
244 */
245enum {
246 BNX2X_ISCSI_ETH_CL_ID_IDX,
247 BNX2X_FCOE_ETH_CL_ID_IDX,
248 BNX2X_MAX_CNIC_ETH_CL_ID_IDX,
249};
250
55#include "bnx2x_hsi.h"
56#include "bnx2x_link.h"
57#include "bnx2x_sp.h"
58#include "bnx2x_dcb.h"
59#include "bnx2x_stats.h"
60
61/* error/debug prints */
62

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244 *
245 */
246enum {
247 BNX2X_ISCSI_ETH_CL_ID_IDX,
248 BNX2X_FCOE_ETH_CL_ID_IDX,
249 BNX2X_MAX_CNIC_ETH_CL_ID_IDX,
250};
251
251#define BNX2X_CNIC_START_ETH_CID 48
252enum {
252#define BNX2X_CNIC_START_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) *\
253 (bp)->max_cos)
253 /* iSCSI L2 */
254 /* iSCSI L2 */
254 BNX2X_ISCSI_ETH_CID = BNX2X_CNIC_START_ETH_CID,
255#define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp))
255 /* FCoE L2 */
256 /* FCoE L2 */
256 BNX2X_FCOE_ETH_CID,
257};
257#define BNX2X_FCOE_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp) + 1)
258
259/** Additional rings budgeting */
260#ifdef BCM_CNIC
261#define CNIC_PRESENT 1
262#define FCOE_PRESENT 1
263#else
264#define CNIC_PRESENT 0
265#define FCOE_PRESENT 0

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271
272#define SM_RX_ID 0
273#define SM_TX_ID 1
274
275/* defines for multiple tx priority indices */
276#define FIRST_TX_ONLY_COS_INDEX 1
277#define FIRST_TX_COS_INDEX 0
278
258
259/** Additional rings budgeting */
260#ifdef BCM_CNIC
261#define CNIC_PRESENT 1
262#define FCOE_PRESENT 1
263#else
264#define CNIC_PRESENT 0
265#define FCOE_PRESENT 0

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271
272#define SM_RX_ID 0
273#define SM_TX_ID 1
274
275/* defines for multiple tx priority indices */
276#define FIRST_TX_ONLY_COS_INDEX 1
277#define FIRST_TX_COS_INDEX 0
278
279/* defines for decodeing the fastpath index and the cos index out of the
280 * transmission queue index
281 */
282#define MAX_TXQS_PER_COS FP_SB_MAX_E1x
283
284#define TXQ_TO_FP(txq_index) ((txq_index) % MAX_TXQS_PER_COS)
285#define TXQ_TO_COS(txq_index) ((txq_index) / MAX_TXQS_PER_COS)
286
287/* rules for calculating the cids of tx-only connections */
279/* rules for calculating the cids of tx-only connections */
288#define CID_TO_FP(cid) ((cid) % MAX_TXQS_PER_COS)
289#define CID_COS_TO_TX_ONLY_CID(cid, cos) (cid + cos * MAX_TXQS_PER_COS)
280#define CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp))
281#define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \
282 (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
290
291/* fp index inside class of service range */
283
284/* fp index inside class of service range */
292#define FP_COS_TO_TXQ(fp, cos) ((fp)->index + cos * MAX_TXQS_PER_COS)
285#define FP_COS_TO_TXQ(fp, cos, bp) \
286 ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
293
287
294/*
295 * 0..15 eth cos0
296 * 16..31 eth cos1 if applicable
297 * 32..47 eth cos2 If applicable
298 * fcoe queue follows eth queues (16, 32, 48 depending on cos)
288/* Indexes for transmission queues array:
289 * txdata for RSS i CoS j is at location i + (j * num of RSS)
290 * txdata for FCoE (if exist) is at location max cos * num of RSS
291 * txdata for FWD (if exist) is one location after FCoE
292 * txdata for OOO (if exist) is one location after FWD
299 */
293 */
300#define MAX_ETH_TXQ_IDX(bp) (MAX_TXQS_PER_COS * (bp)->max_cos)
301#define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp))
294enum {
295 FCOE_TXQ_IDX_OFFSET,
296 FWD_TXQ_IDX_OFFSET,
297 OOO_TXQ_IDX_OFFSET,
298};
299#define MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos)
300#ifdef BCM_CNIC
301#define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET)
302#endif
302
303/* fast path */
304/*
305 * This driver uses new build_skb() API :
306 * RX ring buffer contains pointer to kmalloc() data only,
307 * skb are built only after Hardware filled the frame.
308 */
309struct sw_rx_bd {

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476 u16 tx_bd_prod;
477 u16 tx_bd_cons;
478
479 unsigned long tx_pkt;
480
481 __le16 *tx_cons_sb;
482
483 int txq_index;
303
304/* fast path */
305/*
306 * This driver uses new build_skb() API :
307 * RX ring buffer contains pointer to kmalloc() data only,
308 * skb are built only after Hardware filled the frame.
309 */
310struct sw_rx_bd {

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477 u16 tx_bd_prod;
478 u16 tx_bd_cons;
479
480 unsigned long tx_pkt;
481
482 __le16 *tx_cons_sb;
483
484 int txq_index;
485 struct bnx2x_fastpath *parent_fp;
486 int tx_ring_size;
484};
485
486enum bnx2x_tpa_mode_t {
487 TPA_MODE_LRO,
488 TPA_MODE_GRO
489};
490
491struct bnx2x_fastpath {

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502
503 u32 rx_buf_size;
504
505 dma_addr_t status_blk_mapping;
506
507 enum bnx2x_tpa_mode_t mode;
508
509 u8 max_cos; /* actual number of active tx coses */
487};
488
489enum bnx2x_tpa_mode_t {
490 TPA_MODE_LRO,
491 TPA_MODE_GRO
492};
493
494struct bnx2x_fastpath {

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505
506 u32 rx_buf_size;
507
508 dma_addr_t status_blk_mapping;
509
510 enum bnx2x_tpa_mode_t mode;
511
512 u8 max_cos; /* actual number of active tx coses */
510 struct bnx2x_fp_txdata txdata[BNX2X_MULTI_TX_COS];
513 struct bnx2x_fp_txdata *txdata_ptr[BNX2X_MULTI_TX_COS];
511
512 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
513 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
514
515 struct eth_rx_bd *rx_desc_ring;
516 dma_addr_t rx_desc_mapping;
517
518 union eth_rx_cqe *rx_comp_ring;

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542 u16 rx_sge_prod;
543 /* The last maximal completed SGE */
544 u16 last_max_sge;
545 __le16 *rx_cons_sb;
546 unsigned long rx_pkt,
547 rx_calls;
548
549 /* TPA related */
514
515 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
516 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
517
518 struct eth_rx_bd *rx_desc_ring;
519 dma_addr_t rx_desc_mapping;
520
521 union eth_rx_cqe *rx_comp_ring;

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545 u16 rx_sge_prod;
546 /* The last maximal completed SGE */
547 u16 last_max_sge;
548 __le16 *rx_cons_sb;
549 unsigned long rx_pkt,
550 rx_calls;
551
552 /* TPA related */
550 struct bnx2x_agg_info tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2];
553 struct bnx2x_agg_info *tpa_info;
551 u8 disable_tpa;
552#ifdef BNX2X_STOP_ON_ERROR
553 u64 tpa_queue_used;
554#endif
554 u8 disable_tpa;
555#ifdef BNX2X_STOP_ON_ERROR
556 u64 tpa_queue_used;
557#endif
555
556 struct tstorm_per_queue_stats old_tclient;
557 struct ustorm_per_queue_stats old_uclient;
558 struct xstorm_per_queue_stats old_xclient;
559 struct bnx2x_eth_q_stats eth_q_stats;
560 struct bnx2x_eth_q_stats_old eth_q_stats_old;
561
562 /* The size is calculated using the following:
563 sizeof name field from netdev structure +
564 4 ('-Xx-' string) +
565 4 (for the digits and to make it DWORD aligned) */
566#define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
567 char name[FP_NAME_SIZE];
558 /* The size is calculated using the following:
559 sizeof name field from netdev structure +
560 4 ('-Xx-' string) +
561 4 (for the digits and to make it DWORD aligned) */
562#define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
563 char name[FP_NAME_SIZE];
568
569 /* MACs object */
570 struct bnx2x_vlan_mac_obj mac_obj;
571
572 /* Queue State object */
573 struct bnx2x_queue_sp_obj q_obj;
574
575};
576
564};
565
577#define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
566#define bnx2x_fp(bp, nr, var) ((bp)->fp[(nr)].var)
567#define bnx2x_sp_obj(bp, fp) ((bp)->sp_objs[(fp)->index])
568#define bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index]))
569#define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats))
578
579/* Use 2500 as a mini-jumbo MTU for FCoE */
580#define BNX2X_FCOE_MINI_JUMBO_MTU 2500
581
570
571/* Use 2500 as a mini-jumbo MTU for FCoE */
572#define BNX2X_FCOE_MINI_JUMBO_MTU 2500
573
582/* FCoE L2 `fastpath' entry is right after the eth entries */
583#define FCOE_IDX BNX2X_NUM_ETH_QUEUES(bp)
584#define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX])
585#define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var)
586#define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \
587 txdata[FIRST_TX_COS_INDEX].var)
574#define FCOE_IDX_OFFSET 0
588
575
576#define FCOE_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \
577 FCOE_IDX_OFFSET)
578#define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)])
579#define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var)
580#define bnx2x_fcoe_inner_sp_obj(bp) (&bp->sp_objs[FCOE_IDX(bp)])
581#define bnx2x_fcoe_sp_obj(bp, var) (bnx2x_fcoe_inner_sp_obj(bp)->var)
582#define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \
583 txdata_ptr[FIRST_TX_COS_INDEX] \
584 ->var)
589
585
586
590#define IS_ETH_FP(fp) (fp->index < \
591 BNX2X_NUM_ETH_QUEUES(fp->bp))
592#ifdef BCM_CNIC
587#define IS_ETH_FP(fp) (fp->index < \
588 BNX2X_NUM_ETH_QUEUES(fp->bp))
589#ifdef BCM_CNIC
593#define IS_FCOE_FP(fp) (fp->index == FCOE_IDX)
594#define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX)
590#define IS_FCOE_FP(fp) (fp->index == FCOE_IDX(fp->bp))
591#define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(bp))
595#else
596#define IS_FCOE_FP(fp) false
597#define IS_FCOE_IDX(idx) false
598#endif
599
600
601/* MC hsi */
602#define MAX_FETCH_BD 13 /* HW max BDs per packet */

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973#define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
974
975union cdu_context {
976 struct eth_context eth;
977 char pad[1024];
978};
979
980/* CDU host DB constants */
592#else
593#define IS_FCOE_FP(fp) false
594#define IS_FCOE_IDX(idx) false
595#endif
596
597
598/* MC hsi */
599#define MAX_FETCH_BD 13 /* HW max BDs per packet */

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970#define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
971
972union cdu_context {
973 struct eth_context eth;
974 char pad[1024];
975};
976
977/* CDU host DB constants */
981#define CDU_ILT_PAGE_SZ_HW 3
982#define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 64K */
978#define CDU_ILT_PAGE_SZ_HW 2
979#define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */
983#define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
984
985#ifdef BCM_CNIC
986#define CNIC_ISCSI_CID_MAX 256
987#define CNIC_FCOE_CID_MAX 2048
988#define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
989#define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
990#endif

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1177
1178struct bnx2x_prev_path_list {
1179 u8 bus;
1180 u8 slot;
1181 u8 path;
1182 struct list_head list;
1183};
1184
980#define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
981
982#ifdef BCM_CNIC
983#define CNIC_ISCSI_CID_MAX 256
984#define CNIC_FCOE_CID_MAX 2048
985#define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
986#define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
987#endif

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1174
1175struct bnx2x_prev_path_list {
1176 u8 bus;
1177 u8 slot;
1178 u8 path;
1179 struct list_head list;
1180};
1181
1182struct bnx2x_sp_objs {
1183 /* MACs object */
1184 struct bnx2x_vlan_mac_obj mac_obj;
1185
1186 /* Queue State object */
1187 struct bnx2x_queue_sp_obj q_obj;
1188};
1189
1190struct bnx2x_fp_stats {
1191 struct tstorm_per_queue_stats old_tclient;
1192 struct ustorm_per_queue_stats old_uclient;
1193 struct xstorm_per_queue_stats old_xclient;
1194 struct bnx2x_eth_q_stats eth_q_stats;
1195 struct bnx2x_eth_q_stats_old eth_q_stats_old;
1196};
1197
1185struct bnx2x {
1186 /* Fields used in the tx and intr/napi performance paths
1187 * are grouped together in the beginning of the structure
1188 */
1189 struct bnx2x_fastpath *fp;
1198struct bnx2x {
1199 /* Fields used in the tx and intr/napi performance paths
1200 * are grouped together in the beginning of the structure
1201 */
1202 struct bnx2x_fastpath *fp;
1203 struct bnx2x_sp_objs *sp_objs;
1204 struct bnx2x_fp_stats *fp_stats;
1205 struct bnx2x_fp_txdata *bnx2x_txq;
1206 int bnx2x_txq_size;
1190 void __iomem *regview;
1191 void __iomem *doorbells;
1192 u16 db_size;
1193
1194 u8 pf_num; /* absolute PF number */
1195 u8 pfid; /* per-path PF number */
1196 int base_fw_ndsb; /**/
1197#define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1))

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1296#define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
1297#define GRO_ENABLE_FLAG (1 << 10)
1298#define MF_FUNC_DIS (1 << 11)
1299#define OWN_CNIC_IRQ (1 << 12)
1300#define NO_ISCSI_OOO_FLAG (1 << 13)
1301#define NO_ISCSI_FLAG (1 << 14)
1302#define NO_FCOE_FLAG (1 << 15)
1303#define BC_SUPPORTS_PFC_STATS (1 << 17)
1207 void __iomem *regview;
1208 void __iomem *doorbells;
1209 u16 db_size;
1210
1211 u8 pf_num; /* absolute PF number */
1212 u8 pfid; /* per-path PF number */
1213 int base_fw_ndsb; /**/
1214#define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1))

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1313#define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
1314#define GRO_ENABLE_FLAG (1 << 10)
1315#define MF_FUNC_DIS (1 << 11)
1316#define OWN_CNIC_IRQ (1 << 12)
1317#define NO_ISCSI_OOO_FLAG (1 << 13)
1318#define NO_ISCSI_FLAG (1 << 14)
1319#define NO_FCOE_FLAG (1 << 15)
1320#define BC_SUPPORTS_PFC_STATS (1 << 17)
1321#define BC_SUPPORTS_FCOE_FEATURES (1 << 19)
1304#define USING_SINGLE_MSIX_FLAG (1 << 20)
1322#define USING_SINGLE_MSIX_FLAG (1 << 20)
1323#define BC_SUPPORTS_DCBX_MSG_NON_PMF (1 << 21)
1305
1306#define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG)
1307#define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG)
1308#define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG)
1309
1310 int pm_cap;
1311 int mrrs;
1312

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1372#define BNX2X_STATE_DIAG 0xe000
1373#define BNX2X_STATE_ERROR 0xf000
1374
1375#define BNX2X_MAX_PRIORITY 8
1376#define BNX2X_MAX_ENTRIES_PER_PRI 16
1377#define BNX2X_MAX_COS 3
1378#define BNX2X_MAX_TX_COS 2
1379 int num_queues;
1324
1325#define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG)
1326#define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG)
1327#define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG)
1328
1329 int pm_cap;
1330 int mrrs;
1331

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1391#define BNX2X_STATE_DIAG 0xe000
1392#define BNX2X_STATE_ERROR 0xf000
1393
1394#define BNX2X_MAX_PRIORITY 8
1395#define BNX2X_MAX_ENTRIES_PER_PRI 16
1396#define BNX2X_MAX_COS 3
1397#define BNX2X_MAX_TX_COS 2
1398 int num_queues;
1399 int num_napi_queues;
1380 int disable_tpa;
1381
1382 u32 rx_mode;
1383#define BNX2X_RX_MODE_NONE 0
1384#define BNX2X_RX_MODE_NORMAL 1
1385#define BNX2X_RX_MODE_ALLMULTI 2
1386#define BNX2X_RX_MODE_PROMISC 3
1387#define BNX2X_MAX_MULTICAST 64
1388
1389 u8 igu_dsb_id;
1390 u8 igu_base_sb;
1391 u8 igu_sb_cnt;
1400 int disable_tpa;
1401
1402 u32 rx_mode;
1403#define BNX2X_RX_MODE_NONE 0
1404#define BNX2X_RX_MODE_NORMAL 1
1405#define BNX2X_RX_MODE_ALLMULTI 2
1406#define BNX2X_RX_MODE_PROMISC 3
1407#define BNX2X_MAX_MULTICAST 64
1408
1409 u8 igu_dsb_id;
1410 u8 igu_base_sb;
1411 u8 igu_sb_cnt;
1412
1392 dma_addr_t def_status_blk_mapping;
1393
1394 struct bnx2x_slowpath *slowpath;
1395 dma_addr_t slowpath_mapping;
1396
1397 /* Total number of FW statistics requests */
1398 u8 fw_stats_num;
1399

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1415 /*
1416 * FW statistics data shortcut (points at the begining of
1417 * fw_stats buffer + fw_stats_req_sz).
1418 */
1419 struct bnx2x_fw_stats_data *fw_stats_data;
1420 dma_addr_t fw_stats_data_mapping;
1421 int fw_stats_data_sz;
1422
1413 dma_addr_t def_status_blk_mapping;
1414
1415 struct bnx2x_slowpath *slowpath;
1416 dma_addr_t slowpath_mapping;
1417
1418 /* Total number of FW statistics requests */
1419 u8 fw_stats_num;
1420

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1436 /*
1437 * FW statistics data shortcut (points at the begining of
1438 * fw_stats buffer + fw_stats_req_sz).
1439 */
1440 struct bnx2x_fw_stats_data *fw_stats_data;
1441 dma_addr_t fw_stats_data_mapping;
1442 int fw_stats_data_sz;
1443
1423 struct hw_context context;
1444 /* For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB
1445 * context size we need 8 ILT entries.
1446 */
1447#define ILT_MAX_L2_LINES 8
1448 struct hw_context context[ILT_MAX_L2_LINES];
1424
1425 struct bnx2x_ilt *ilt;
1426#define BP_ILT(bp) ((bp)->ilt)
1427#define ILT_MAX_LINES 256
1428/*
1429 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes
1430 * to CNIC.
1431 */
1432#define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_PRESENT)
1433
1434/*
1435 * Maximum CID count that might be required by the bnx2x:
1449
1450 struct bnx2x_ilt *ilt;
1451#define BP_ILT(bp) ((bp)->ilt)
1452#define ILT_MAX_LINES 256
1453/*
1454 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes
1455 * to CNIC.
1456 */
1457#define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_PRESENT)
1458
1459/*
1460 * Maximum CID count that might be required by the bnx2x:
1436 * Max Tss * Max_Tx_Multi_Cos + CNIC L2 Clients (FCoE and iSCSI related)
1461 * Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI
1437 */
1462 */
1438#define BNX2X_L2_CID_COUNT(bp) (MAX_TXQS_PER_COS * BNX2X_MULTI_TX_COS +\
1439 NON_ETH_CONTEXT_USE + CNIC_PRESENT)
1463#define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \
1464 + NON_ETH_CONTEXT_USE + CNIC_PRESENT)
1465#define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \
1466 + NON_ETH_CONTEXT_USE + CNIC_PRESENT)
1440#define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\
1441 ILT_PAGE_CIDS))
1467#define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\
1468 ILT_PAGE_CIDS))
1442#define BNX2X_DB_SIZE(bp) (BNX2X_L2_CID_COUNT(bp) * (1 << BNX2X_DB_SHIFT))
1443
1444 int qm_cid_count;
1445
1446 int dropless_fc;
1447
1448#ifdef BCM_CNIC
1449 u32 cnic_flags;
1450#define BNX2X_CNIC_FLAG_MAC_SET 1

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1593 /* priority to cos mapping */
1594 u8 prio_to_cos[8];
1595};
1596
1597/* Tx queues may be less or equal to Rx queues */
1598extern int num_queues;
1599#define BNX2X_NUM_QUEUES(bp) (bp->num_queues)
1600#define BNX2X_NUM_ETH_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - NON_ETH_CONTEXT_USE)
1469
1470 int qm_cid_count;
1471
1472 int dropless_fc;
1473
1474#ifdef BCM_CNIC
1475 u32 cnic_flags;
1476#define BNX2X_CNIC_FLAG_MAC_SET 1

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1619 /* priority to cos mapping */
1620 u8 prio_to_cos[8];
1621};
1622
1623/* Tx queues may be less or equal to Rx queues */
1624extern int num_queues;
1625#define BNX2X_NUM_QUEUES(bp) (bp->num_queues)
1626#define BNX2X_NUM_ETH_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - NON_ETH_CONTEXT_USE)
1627#define BNX2X_NUM_NON_CNIC_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - \
1628 NON_ETH_CONTEXT_USE)
1601#define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp)
1602
1603#define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
1604
1605#define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp)
1606/* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */
1607
1608#define RSS_IPV4_CAP_MASK \

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1651
1652/* Skip forwarding FP */
1653#define for_each_rx_queue(bp, var) \
1654 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1655 if (skip_rx_queue(bp, var)) \
1656 continue; \
1657 else
1658
1629#define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp)
1630
1631#define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
1632
1633#define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp)
1634/* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */
1635
1636#define RSS_IPV4_CAP_MASK \

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1679
1680/* Skip forwarding FP */
1681#define for_each_rx_queue(bp, var) \
1682 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1683 if (skip_rx_queue(bp, var)) \
1684 continue; \
1685 else
1686
1687#define for_each_napi_rx_queue(bp, var) \
1688 for ((var) = 0; (var) < bp->num_napi_queues; (var)++)
1689
1659/* Skip OOO FP */
1660#define for_each_tx_queue(bp, var) \
1661 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1662 if (skip_tx_queue(bp, var)) \
1663 continue; \
1664 else
1665
1666#define for_each_nondefault_queue(bp, var) \

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1812 */
1813#define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
1814#define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
1815
1816/* load/unload mode */
1817#define LOAD_NORMAL 0
1818#define LOAD_OPEN 1
1819#define LOAD_DIAG 2
1690/* Skip OOO FP */
1691#define for_each_tx_queue(bp, var) \
1692 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1693 if (skip_tx_queue(bp, var)) \
1694 continue; \
1695 else
1696
1697#define for_each_nondefault_queue(bp, var) \

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1843 */
1844#define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
1845#define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
1846
1847/* load/unload mode */
1848#define LOAD_NORMAL 0
1849#define LOAD_OPEN 1
1850#define LOAD_DIAG 2
1851#define LOAD_LOOPBACK_EXT 3
1820#define UNLOAD_NORMAL 0
1821#define UNLOAD_CLOSE 1
1822#define UNLOAD_RECOVERY 2
1823
1824
1825/* DMAE command defines */
1826#define DMAE_TIMEOUT -1
1827#define DMAE_PCI_ERROR -2 /* E2 and onward */

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1894 E1HVN_MAX)
1895
1896/* PCIE link and speed */
1897#define PCICFG_LINK_WIDTH 0x1f00000
1898#define PCICFG_LINK_WIDTH_SHIFT 20
1899#define PCICFG_LINK_SPEED 0xf0000
1900#define PCICFG_LINK_SPEED_SHIFT 16
1901
1852#define UNLOAD_NORMAL 0
1853#define UNLOAD_CLOSE 1
1854#define UNLOAD_RECOVERY 2
1855
1856
1857/* DMAE command defines */
1858#define DMAE_TIMEOUT -1
1859#define DMAE_PCI_ERROR -2 /* E2 and onward */

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1926 E1HVN_MAX)
1927
1928/* PCIE link and speed */
1929#define PCICFG_LINK_WIDTH 0x1f00000
1930#define PCICFG_LINK_WIDTH_SHIFT 20
1931#define PCICFG_LINK_SPEED 0xf0000
1932#define PCICFG_LINK_SPEED_SHIFT 16
1933
1934#define BNX2X_NUM_TESTS_SF 7
1935#define BNX2X_NUM_TESTS_MF 3
1936#define BNX2X_NUM_TESTS(bp) (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \
1937 BNX2X_NUM_TESTS_SF)
1902
1938
1903#define BNX2X_NUM_TESTS 7
1904
1905#define BNX2X_PHY_LOOPBACK 0
1906#define BNX2X_MAC_LOOPBACK 1
1939#define BNX2X_PHY_LOOPBACK 0
1940#define BNX2X_MAC_LOOPBACK 1
1941#define BNX2X_EXT_LOOPBACK 2
1907#define BNX2X_PHY_LOOPBACK_FAILED 1
1908#define BNX2X_MAC_LOOPBACK_FAILED 2
1942#define BNX2X_PHY_LOOPBACK_FAILED 1
1943#define BNX2X_MAC_LOOPBACK_FAILED 2
1944#define BNX2X_EXT_LOOPBACK_FAILED 3
1909#define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
1910 BNX2X_PHY_LOOPBACK_FAILED)
1911
1912
1913#define STROM_ASSERT_ARRAY_SIZE 50
1914
1915
1916/* must be used on a CID before placing it on a HW ring */

--- 240 unchanged lines hidden --- 		1945#define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
1946 BNX2X_PHY_LOOPBACK_FAILED)
1947
1948
1949#define STROM_ASSERT_ARRAY_SIZE 50
1950
1951
1952/* must be used on a CID before placing it on a HW ring */

--- 240 unchanged lines hidden ---