bnx2x.h (8c57a5e7b2820f349c95b8c8393fec1e0f4070d2) bnx2x.h (e1c6dccaf3af291488fbad155d7ee6bc29db262a)
1/* bnx2x.h: QLogic Everest network driver.
2 *
3 * Copyright (c) 2007-2013 Broadcom Corporation
4 * Copyright (c) 2014 QLogic Corporation
5 * All rights reserved
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by

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1391
1392 enum bnx2x_recovery_state recovery_state;
1393 int is_leader;
1394 struct msix_entry *msix_table;
1395
1396 int tx_ring_size;
1397
1398/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
1/* bnx2x.h: QLogic Everest network driver.
2 *
3 * Copyright (c) 2007-2013 Broadcom Corporation
4 * Copyright (c) 2014 QLogic Corporation
5 * All rights reserved
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by

--- 1382 unchanged lines hidden (view full) ---

1391
1392 enum bnx2x_recovery_state recovery_state;
1393 int is_leader;
1394 struct msix_entry *msix_table;
1395
1396 int tx_ring_size;
1397
1398/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
1399#define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
1400#define ETH_MIN_PACKET_SIZE 60
1401#define ETH_MAX_PACKET_SIZE 1500
1399#define ETH_OVERHEAD (ETH_HLEN + 8 + 8)
1400#define ETH_MIN_PACKET_SIZE (ETH_ZLEN - ETH_HLEN)
1401#define ETH_MAX_PACKET_SIZE ETH_DATA_LEN
1402#define ETH_MAX_JUMBO_PACKET_SIZE 9600
1403/* TCP with Timestamp Option (32) + IPv6 (40) */
1404#define ETH_MAX_TPA_HEADER_SIZE 72
1405
1406 /* Max supported alignment is 256 (8 shift)
1407 * minimal alignment shift 6 is optimal for 57xxx HW performance
1408 */
1409#define BNX2X_RX_ALIGN_SHIFT max(6, min(8, L1_CACHE_SHIFT))

--- 1111 unchanged lines hidden --- 		1402#define ETH_MAX_JUMBO_PACKET_SIZE 9600
1403/* TCP with Timestamp Option (32) + IPv6 (40) */
1404#define ETH_MAX_TPA_HEADER_SIZE 72
1405
1406 /* Max supported alignment is 256 (8 shift)
1407 * minimal alignment shift 6 is optimal for 57xxx HW performance
1408 */
1409#define BNX2X_RX_ALIGN_SHIFT max(6, min(8, L1_CACHE_SHIFT))

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