bnx2.c (aea983801c6b5e4e9af333a32220d580a77f6783) bnx2.c (e1c6dccaf3af291488fbad155d7ee6bc29db262a)
1/* bnx2.c: QLogic bnx2 network driver.
2 *
3 * Copyright (c) 2004-2014 Broadcom Corporation
4 * Copyright (c) 2014-2015 QLogic Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.

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2293 if (reset_phy)
2294 bnx2_reset_phy(bp);
2295
2296 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
2297
2298 if (BNX2_CHIP(bp) == BNX2_CHIP_5706)
2299 BNX2_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
2300
1/* bnx2.c: QLogic bnx2 network driver.
2 *
3 * Copyright (c) 2004-2014 Broadcom Corporation
4 * Copyright (c) 2014-2015 QLogic Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.

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2293 if (reset_phy)
2294 bnx2_reset_phy(bp);
2295
2296 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
2297
2298 if (BNX2_CHIP(bp) == BNX2_CHIP_5706)
2299 BNX2_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
2300
2301 if (bp->dev->mtu > 1500) {
2301 if (bp->dev->mtu > ETH_DATA_LEN) {
2302 u32 val;
2303
2304 /* Set extended packet length bit */
2305 bnx2_write_phy(bp, 0x18, 0x7);
2306 bnx2_read_phy(bp, 0x18, &val);
2307 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2308
2309 bnx2_write_phy(bp, 0x1c, 0x6c00);

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2347 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
2348 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2349 MII_BNX2_DSP_EXPAND_REG | 0x8);
2350 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2351 val &= ~(1 << 8);
2352 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2353 }
2354
2302 u32 val;
2303
2304 /* Set extended packet length bit */
2305 bnx2_write_phy(bp, 0x18, 0x7);
2306 bnx2_read_phy(bp, 0x18, &val);
2307 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2308
2309 bnx2_write_phy(bp, 0x1c, 0x6c00);

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2347 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
2348 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2349 MII_BNX2_DSP_EXPAND_REG | 0x8);
2350 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2351 val &= ~(1 << 8);
2352 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2353 }
2354
2355 if (bp->dev->mtu > 1500) {
2355 if (bp->dev->mtu > ETH_DATA_LEN) {
2356 /* Set extended packet length bit */
2357 bnx2_write_phy(bp, 0x18, 0x7);
2358 bnx2_read_phy(bp, 0x18, &val);
2359 bnx2_write_phy(bp, 0x18, val | 0x4000);
2360
2361 bnx2_read_phy(bp, 0x10, &val);
2362 bnx2_write_phy(bp, 0x10, val | 0x1);
2363 }

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4980 bp->mac_addr[3] +
4981 (bp->mac_addr[4] << 8) +
4982 (bp->mac_addr[5] << 16);
4983 BNX2_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4984
4985 /* Program the MTU. Also include 4 bytes for CRC32. */
4986 mtu = bp->dev->mtu;
4987 val = mtu + ETH_HLEN + ETH_FCS_LEN;
2356 /* Set extended packet length bit */
2357 bnx2_write_phy(bp, 0x18, 0x7);
2358 bnx2_read_phy(bp, 0x18, &val);
2359 bnx2_write_phy(bp, 0x18, val | 0x4000);
2360
2361 bnx2_read_phy(bp, 0x10, &val);
2362 bnx2_write_phy(bp, 0x10, val | 0x1);
2363 }

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4980 bp->mac_addr[3] +
4981 (bp->mac_addr[4] << 8) +
4982 (bp->mac_addr[5] << 16);
4983 BNX2_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4984
4985 /* Program the MTU. Also include 4 bytes for CRC32. */
4986 mtu = bp->dev->mtu;
4987 val = mtu + ETH_HLEN + ETH_FCS_LEN;
4988 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4988 if (val > (MAX_ETHERNET_PACKET_SIZE + ETH_HLEN + 4))
4989 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4990 BNX2_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4991
4989 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4990 BNX2_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4991
4992 if (mtu < 1500)
4993 mtu = 1500;
4992 if (mtu < ETH_DATA_LEN)
4993 mtu = ETH_DATA_LEN;
4994
4995 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
4996 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
4997 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
4998
4999 memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size);
5000 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
5001 bp->bnx2_napi[i].last_status_idx = 0;

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7891}
7892
7893/* Called with rtnl_lock */
7894static int
7895bnx2_change_mtu(struct net_device *dev, int new_mtu)
7896{
7897 struct bnx2 *bp = netdev_priv(dev);
7898
4994
4995 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
4996 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
4997 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
4998
4999 memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size);
5000 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
5001 bp->bnx2_napi[i].last_status_idx = 0;

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7891}
7892
7893/* Called with rtnl_lock */
7894static int
7895bnx2_change_mtu(struct net_device *dev, int new_mtu)
7896{
7897 struct bnx2 *bp = netdev_priv(dev);
7898
7899 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
7900 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
7901 return -EINVAL;
7902
7903 dev->mtu = new_mtu;
7904 return bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size,
7905 false);
7906}
7907
7908#ifdef CONFIG_NET_POLL_CONTROLLER
7909static void
7910poll_bnx2(struct net_device *dev)

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8584
8585 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
8586 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8587
8588 dev->vlan_features = dev->hw_features;
8589 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
8590 dev->features |= dev->hw_features;
8591 dev->priv_flags |= IFF_UNICAST_FLT;
7899 dev->mtu = new_mtu;
7900 return bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size,
7901 false);
7902}
7903
7904#ifdef CONFIG_NET_POLL_CONTROLLER
7905static void
7906poll_bnx2(struct net_device *dev)

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8580
8581 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
8582 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8583
8584 dev->vlan_features = dev->hw_features;
8585 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
8586 dev->features |= dev->hw_features;
8587 dev->priv_flags |= IFF_UNICAST_FLT;
8588 dev->min_mtu = MIN_ETHERNET_PACKET_SIZE;
8589 dev->max_mtu = MAX_ETHERNET_JUMBO_PACKET_SIZE;
8592
8593 if (!(bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
8594 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
8595
8596 if ((rc = register_netdev(dev))) {
8597 dev_err(&pdev->dev, "Cannot register net device\n");
8598 goto error;
8599 }

--- 239 unchanged lines hidden --- 		8590
8591 if (!(bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
8592 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
8593
8594 if ((rc = register_netdev(dev))) {
8595 dev_err(&pdev->dev, "Cannot register net device\n");
8596 goto error;
8597 }

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