felix.h (6f84981772535e670e4e2df051a672af229b6694) felix.h (1dc6a2a02320dab136c5f2e94b39dbb85f9e698c)
1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright 2019 NXP
3 */
4#ifndef _MSCC_FELIX_H
5#define _MSCC_FELIX_H
6
7#define ocelot_to_felix(o) container_of((o), struct felix, ocelot)
8#define FELIX_MAC_QUIRKS OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION

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31 int num_ports;
32 int num_tx_queues;
33 struct vcap_props *vcap;
34 u16 vcap_pol_base;
35 u16 vcap_pol_max;
36 u16 vcap_pol_base2;
37 u16 vcap_pol_max2;
38 const struct ptp_clock_info *ptp_caps;
1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright 2019 NXP
3 */
4#ifndef _MSCC_FELIX_H
5#define _MSCC_FELIX_H
6
7#define ocelot_to_felix(o) container_of((o), struct felix, ocelot)
8#define FELIX_MAC_QUIRKS OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION

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31 int num_ports;
32 int num_tx_queues;
33 struct vcap_props *vcap;
34 u16 vcap_pol_base;
35 u16 vcap_pol_max;
36 u16 vcap_pol_base2;
37 u16 vcap_pol_max2;
38 const struct ptp_clock_info *ptp_caps;
39 unsigned long quirks;
39
40 /* Some Ocelot switches are integrated into the SoC without the
41 * extraction IRQ line connected to the ARM GIC. By enabling this
42 * workaround, the few packets that are delivered to the CPU port
43 * module (currently only PTP) are copied not only to the hardware CPU
44 * port module, but also to the 802.1Q Ethernet CPU port, and polling
45 * the extraction registers is triggered once the DSA tagger sees a PTP
46 * frame. The Ethernet frame is only used as a notification: it is

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41 /* Some Ocelot switches are integrated into the SoC without the
42 * extraction IRQ line connected to the ARM GIC. By enabling this
43 * workaround, the few packets that are delivered to the CPU port
44 * module (currently only PTP) are copied not only to the hardware CPU
45 * port module, but also to the 802.1Q Ethernet CPU port, and polling
46 * the extraction registers is triggered once the DSA tagger sees a PTP
47 * frame. The Ethernet frame is only used as a notification: it is

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