dc21285.c (2fc2991175bf77395e6b15fe6b2304d3bf72da40) | dc21285.c (69f34c98c1416eb74c55e38a21dbf3e294966514) |
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1/* 2 * MTD map driver for flash on the DC21285 (the StrongARM-110 companion chip) 3 * 4 * (C) 2000 Nicolas Pitre <nico@cam.org> 5 * 6 * This code is GPL | 1/* 2 * MTD map driver for flash on the DC21285 (the StrongARM-110 companion chip) 3 * 4 * (C) 2000 Nicolas Pitre <nico@cam.org> 5 * 6 * This code is GPL |
7 * 8 * $Id: dc21285.c,v 1.22 2004/11/01 13:39:21 rmk Exp $ | 7 * 8 * $Id: dc21285.c,v 1.24 2005/11/07 11:14:26 gleixner Exp $ |
9 */ 10#include <linux/config.h> 11#include <linux/module.h> 12#include <linux/types.h> 13#include <linux/kernel.h> 14#include <linux/init.h> 15#include <linux/delay.h> 16#include <linux/slab.h> --- 5 unchanged lines hidden (view full) --- 22#include <asm/io.h> 23#include <asm/hardware/dec21285.h> 24#include <asm/mach-types.h> 25 26 27static struct mtd_info *dc21285_mtd; 28 29#ifdef CONFIG_ARCH_NETWINDER | 9 */ 10#include <linux/config.h> 11#include <linux/module.h> 12#include <linux/types.h> 13#include <linux/kernel.h> 14#include <linux/init.h> 15#include <linux/delay.h> 16#include <linux/slab.h> --- 5 unchanged lines hidden (view full) --- 22#include <asm/io.h> 23#include <asm/hardware/dec21285.h> 24#include <asm/mach-types.h> 25 26 27static struct mtd_info *dc21285_mtd; 28 29#ifdef CONFIG_ARCH_NETWINDER |
30/* | 30/* |
31 * This is really ugly, but it seams to be the only | 31 * This is really ugly, but it seams to be the only |
32 * realiable way to do it, as the cpld state machine | 32 * realiable way to do it, as the cpld state machine |
33 * is unpredictible. So we have a 25us penalty per 34 * write access. 35 */ 36static void nw_en_write(void) 37{ 38 extern spinlock_t gpio_lock; 39 unsigned long flags; 40 --- 104 unchanged lines hidden (view full) --- 145}; 146 147 148/* Partition stuff */ 149#ifdef CONFIG_MTD_PARTITIONS 150static struct mtd_partition *dc21285_parts; 151static const char *probes[] = { "RedBoot", "cmdlinepart", NULL }; 152#endif | 33 * is unpredictible. So we have a 25us penalty per 34 * write access. 35 */ 36static void nw_en_write(void) 37{ 38 extern spinlock_t gpio_lock; 39 unsigned long flags; 40 --- 104 unchanged lines hidden (view full) --- 145}; 146 147 148/* Partition stuff */ 149#ifdef CONFIG_MTD_PARTITIONS 150static struct mtd_partition *dc21285_parts; 151static const char *probes[] = { "RedBoot", "cmdlinepart", NULL }; 152#endif |
153 | 153 |
154static int __init init_dc21285(void) 155{ 156 157#ifdef CONFIG_MTD_PARTITIONS 158 int nrparts; 159#endif 160 161 /* Determine bankwidth */ 162 switch (*CSR_SA110_CNTL & (3<<14)) { | 154static int __init init_dc21285(void) 155{ 156 157#ifdef CONFIG_MTD_PARTITIONS 158 int nrparts; 159#endif 160 161 /* Determine bankwidth */ 162 switch (*CSR_SA110_CNTL & (3<<14)) { |
163 case SA110_CNTL_ROMWIDTH_8: | 163 case SA110_CNTL_ROMWIDTH_8: |
164 dc21285_map.bankwidth = 1; 165 dc21285_map.read = dc21285_read8; 166 dc21285_map.write = dc21285_write8; 167 dc21285_map.copy_to = dc21285_copy_to_8; 168 break; | 164 dc21285_map.bankwidth = 1; 165 dc21285_map.read = dc21285_read8; 166 dc21285_map.write = dc21285_write8; 167 dc21285_map.copy_to = dc21285_copy_to_8; 168 break; |
169 case SA110_CNTL_ROMWIDTH_16: 170 dc21285_map.bankwidth = 2; | 169 case SA110_CNTL_ROMWIDTH_16: 170 dc21285_map.bankwidth = 2; |
171 dc21285_map.read = dc21285_read16; 172 dc21285_map.write = dc21285_write16; 173 dc21285_map.copy_to = dc21285_copy_to_16; 174 break; | 171 dc21285_map.read = dc21285_read16; 172 dc21285_map.write = dc21285_write16; 173 dc21285_map.copy_to = dc21285_copy_to_16; 174 break; |
175 case SA110_CNTL_ROMWIDTH_32: 176 dc21285_map.bankwidth = 4; | 175 case SA110_CNTL_ROMWIDTH_32: 176 dc21285_map.bankwidth = 4; |
177 dc21285_map.read = dc21285_read32; 178 dc21285_map.write = dc21285_write32; 179 dc21285_map.copy_to = dc21285_copy_to_32; 180 break; 181 default: 182 printk (KERN_ERR "DC21285 flash: undefined bankwidth\n"); 183 return -ENXIO; 184 } --- 11 unchanged lines hidden (view full) --- 196 dc21285_mtd = do_map_probe("cfi_probe", &dc21285_map); 197 } else { 198 dc21285_mtd = do_map_probe("jedec_probe", &dc21285_map); 199 } 200 201 if (!dc21285_mtd) { 202 iounmap(dc21285_map.virt); 203 return -ENXIO; | 177 dc21285_map.read = dc21285_read32; 178 dc21285_map.write = dc21285_write32; 179 dc21285_map.copy_to = dc21285_copy_to_32; 180 break; 181 default: 182 printk (KERN_ERR "DC21285 flash: undefined bankwidth\n"); 183 return -ENXIO; 184 } --- 11 unchanged lines hidden (view full) --- 196 dc21285_mtd = do_map_probe("cfi_probe", &dc21285_map); 197 } else { 198 dc21285_mtd = do_map_probe("jedec_probe", &dc21285_map); 199 } 200 201 if (!dc21285_mtd) { 202 iounmap(dc21285_map.virt); 203 return -ENXIO; |
204 } 205 | 204 } 205 |
206 dc21285_mtd->owner = THIS_MODULE; 207 208#ifdef CONFIG_MTD_PARTITIONS 209 nrparts = parse_mtd_partitions(dc21285_mtd, probes, &dc21285_parts, 0); 210 if (nrparts > 0) 211 add_mtd_partitions(dc21285_mtd, dc21285_parts, nrparts); | 206 dc21285_mtd->owner = THIS_MODULE; 207 208#ifdef CONFIG_MTD_PARTITIONS 209 nrparts = parse_mtd_partitions(dc21285_mtd, probes, &dc21285_parts, 0); 210 if (nrparts > 0) 211 add_mtd_partitions(dc21285_mtd, dc21285_parts, nrparts); |
212 else 213#endif | 212 else 213#endif |
214 add_mtd_device(dc21285_mtd); | 214 add_mtd_device(dc21285_mtd); |
215 | 215 |
216 if(machine_is_ebsa285()) { | 216 if(machine_is_ebsa285()) { |
217 /* | 217 /* |
218 * Flash timing is determined with bits 19-16 of the 219 * CSR_SA110_CNTL. The value is the number of wait cycles, or 220 * 0 for 16 cycles (the default). Cycles are 20 ns. 221 * Here we use 7 for 140 ns flash chips. 222 */ 223 /* access time */ 224 *CSR_SA110_CNTL = ((*CSR_SA110_CNTL & ~0x000f0000) | (7 << 16)); 225 /* burst time */ 226 *CSR_SA110_CNTL = ((*CSR_SA110_CNTL & ~0x00f00000) | (7 << 20)); 227 /* tristate time */ 228 *CSR_SA110_CNTL = ((*CSR_SA110_CNTL & ~0x0f000000) | (7 << 24)); 229 } | 218 * Flash timing is determined with bits 19-16 of the 219 * CSR_SA110_CNTL. The value is the number of wait cycles, or 220 * 0 for 16 cycles (the default). Cycles are 20 ns. 221 * Here we use 7 for 140 ns flash chips. 222 */ 223 /* access time */ 224 *CSR_SA110_CNTL = ((*CSR_SA110_CNTL & ~0x000f0000) | (7 << 16)); 225 /* burst time */ 226 *CSR_SA110_CNTL = ((*CSR_SA110_CNTL & ~0x00f00000) | (7 << 20)); 227 /* tristate time */ 228 *CSR_SA110_CNTL = ((*CSR_SA110_CNTL & ~0x0f000000) | (7 << 24)); 229 } |
230 | 230 |
231 return 0; 232} 233 234static void __exit cleanup_dc21285(void) 235{ 236#ifdef CONFIG_MTD_PARTITIONS 237 if (dc21285_parts) { 238 del_mtd_partitions(dc21285_mtd); --- 16 unchanged lines hidden --- | 231 return 0; 232} 233 234static void __exit cleanup_dc21285(void) 235{ 236#ifdef CONFIG_MTD_PARTITIONS 237 if (dc21285_parts) { 238 del_mtd_partitions(dc21285_mtd); --- 16 unchanged lines hidden --- |