sdhci.h (e9fb05d5bca7428f2749d059559e9657c710fe53) sdhci.h (162d6f98005fce408efc5af73956c434ae08ef73)
1/*
2 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
3 *
4 * Header file for Host Controller registers and I/O accessors.
5 *
6 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify

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156
157#define SDHCI_HOST_CONTROL2 0x3E
158#define SDHCI_CTRL_UHS_MASK 0x0007
159#define SDHCI_CTRL_UHS_SDR12 0x0000
160#define SDHCI_CTRL_UHS_SDR25 0x0001
161#define SDHCI_CTRL_UHS_SDR50 0x0002
162#define SDHCI_CTRL_UHS_SDR104 0x0003
163#define SDHCI_CTRL_UHS_DDR50 0x0004
1/*
2 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
3 *
4 * Header file for Host Controller registers and I/O accessors.
5 *
6 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify

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156
157#define SDHCI_HOST_CONTROL2 0x3E
158#define SDHCI_CTRL_UHS_MASK 0x0007
159#define SDHCI_CTRL_UHS_SDR12 0x0000
160#define SDHCI_CTRL_UHS_SDR25 0x0001
161#define SDHCI_CTRL_UHS_SDR50 0x0002
162#define SDHCI_CTRL_UHS_SDR104 0x0003
163#define SDHCI_CTRL_UHS_DDR50 0x0004
164#define SDHCI_CTRL_HS400 0x0005 /* Non-standard */
164#define SDHCI_CTRL_HS_SDR200 0x0005 /* reserved value in SDIO spec */
165#define SDHCI_CTRL_VDD_180 0x0008
166#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
167#define SDHCI_CTRL_DRV_TYPE_B 0x0000
168#define SDHCI_CTRL_DRV_TYPE_A 0x0010
169#define SDHCI_CTRL_DRV_TYPE_C 0x0020
170#define SDHCI_CTRL_DRV_TYPE_D 0x0030
171#define SDHCI_CTRL_EXEC_TUNING 0x0040
172#define SDHCI_CTRL_TUNED_CLK 0x0080

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199#define SDHCI_DRIVER_TYPE_D 0x00000040
200#define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00
201#define SDHCI_RETUNING_TIMER_COUNT_SHIFT 8
202#define SDHCI_USE_SDR50_TUNING 0x00002000
203#define SDHCI_RETUNING_MODE_MASK 0x0000C000
204#define SDHCI_RETUNING_MODE_SHIFT 14
205#define SDHCI_CLOCK_MUL_MASK 0x00FF0000
206#define SDHCI_CLOCK_MUL_SHIFT 16
165#define SDHCI_CTRL_VDD_180 0x0008
166#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
167#define SDHCI_CTRL_DRV_TYPE_B 0x0000
168#define SDHCI_CTRL_DRV_TYPE_A 0x0010
169#define SDHCI_CTRL_DRV_TYPE_C 0x0020
170#define SDHCI_CTRL_DRV_TYPE_D 0x0030
171#define SDHCI_CTRL_EXEC_TUNING 0x0040
172#define SDHCI_CTRL_TUNED_CLK 0x0080

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199#define SDHCI_DRIVER_TYPE_D 0x00000040
200#define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00
201#define SDHCI_RETUNING_TIMER_COUNT_SHIFT 8
202#define SDHCI_USE_SDR50_TUNING 0x00002000
203#define SDHCI_RETUNING_MODE_MASK 0x0000C000
204#define SDHCI_RETUNING_MODE_SHIFT 14
205#define SDHCI_CLOCK_MUL_MASK 0x00FF0000
206#define SDHCI_CLOCK_MUL_SHIFT 16
207#define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */
208
209#define SDHCI_CAPABILITIES_1 0x44
210
211#define SDHCI_MAX_CURRENT 0x48
212#define SDHCI_MAX_CURRENT_LIMIT 0xFF
213#define SDHCI_MAX_CURRENT_330_MASK 0x0000FF
214#define SDHCI_MAX_CURRENT_330_SHIFT 0
215#define SDHCI_MAX_CURRENT_300_MASK 0x00FF00

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223#define SDHCI_SET_ACMD12_ERROR 0x50
224#define SDHCI_SET_INT_ERROR 0x52
225
226#define SDHCI_ADMA_ERROR 0x54
227
228/* 55-57 reserved */
229
230#define SDHCI_ADMA_ADDRESS 0x58
207
208#define SDHCI_CAPABILITIES_1 0x44
209
210#define SDHCI_MAX_CURRENT 0x48
211#define SDHCI_MAX_CURRENT_LIMIT 0xFF
212#define SDHCI_MAX_CURRENT_330_MASK 0x0000FF
213#define SDHCI_MAX_CURRENT_330_SHIFT 0
214#define SDHCI_MAX_CURRENT_300_MASK 0x00FF00

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222#define SDHCI_SET_ACMD12_ERROR 0x50
223#define SDHCI_SET_INT_ERROR 0x52
224
225#define SDHCI_ADMA_ERROR 0x54
226
227/* 55-57 reserved */
228
229#define SDHCI_ADMA_ADDRESS 0x58
231#define SDHCI_ADMA_ADDRESS_HI 0x5C
232
233/* 60-FB reserved */
234
235#define SDHCI_PRESET_FOR_SDR12 0x66
236#define SDHCI_PRESET_FOR_SDR25 0x68
237#define SDHCI_PRESET_FOR_SDR50 0x6A
238#define SDHCI_PRESET_FOR_SDR104 0x6C
239#define SDHCI_PRESET_FOR_DDR50 0x6E
230
231/* 60-FB reserved */
232
233#define SDHCI_PRESET_FOR_SDR12 0x66
234#define SDHCI_PRESET_FOR_SDR25 0x68
235#define SDHCI_PRESET_FOR_SDR50 0x6A
236#define SDHCI_PRESET_FOR_SDR104 0x6C
237#define SDHCI_PRESET_FOR_DDR50 0x6E
240#define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */
241#define SDHCI_PRESET_DRV_MASK 0xC000
242#define SDHCI_PRESET_DRV_SHIFT 14
243#define SDHCI_PRESET_CLKGEN_SEL_MASK 0x400
244#define SDHCI_PRESET_CLKGEN_SEL_SHIFT 10
245#define SDHCI_PRESET_SDCLK_FREQ_MASK 0x3FF
246#define SDHCI_PRESET_SDCLK_FREQ_SHIFT 0
247
248#define SDHCI_SLOT_INT_STATUS 0xFC

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264#define SDHCI_MAX_DIV_SPEC_300 2046
265
266/*
267 * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
268 */
269#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
270#define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
271
238#define SDHCI_PRESET_DRV_MASK 0xC000
239#define SDHCI_PRESET_DRV_SHIFT 14
240#define SDHCI_PRESET_CLKGEN_SEL_MASK 0x400
241#define SDHCI_PRESET_CLKGEN_SEL_SHIFT 10
242#define SDHCI_PRESET_SDCLK_FREQ_MASK 0x3FF
243#define SDHCI_PRESET_SDCLK_FREQ_SHIFT 0
244
245#define SDHCI_SLOT_INT_STATUS 0xFC

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261#define SDHCI_MAX_DIV_SPEC_300 2046
262
263/*
264 * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
265 */
266#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
267#define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
268
272/* ADMA2 32-bit DMA descriptor size */
273#define SDHCI_ADMA2_32_DESC_SZ 8
274
275/* ADMA2 32-bit DMA alignment */
276#define SDHCI_ADMA2_32_ALIGN 4
277
278/* ADMA2 32-bit descriptor */
279struct sdhci_adma2_32_desc {
280 __le16 cmd;
281 __le16 len;
282 __le32 addr;
283} __packed __aligned(SDHCI_ADMA2_32_ALIGN);
284
285/* ADMA2 64-bit DMA descriptor size */
286#define SDHCI_ADMA2_64_DESC_SZ 12
287
288/* ADMA2 64-bit DMA alignment */
289#define SDHCI_ADMA2_64_ALIGN 8
290
291/*
292 * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte
293 * aligned.
294 */
295struct sdhci_adma2_64_desc {
296 __le16 cmd;
297 __le16 len;
298 __le32 addr_lo;
299 __le32 addr_hi;
300} __packed __aligned(4);
301
302#define ADMA2_TRAN_VALID 0x21
303#define ADMA2_NOP_END_VALID 0x3
304#define ADMA2_END 0x2
305
306/*
307 * Maximum segments assuming a 512KiB maximum requisition size and a minimum
308 * 4KiB page size.
309 */
310#define SDHCI_MAX_SEGS 128
311
312struct sdhci_ops {
313#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
314 u32 (*read_l)(struct sdhci_host *host, int reg);
315 u16 (*read_w)(struct sdhci_host *host, int reg);
316 u8 (*read_b)(struct sdhci_host *host, int reg);
317 void (*write_l)(struct sdhci_host *host, u32 val, int reg);
318 void (*write_w)(struct sdhci_host *host, u16 val, int reg);
319 void (*write_b)(struct sdhci_host *host, u8 val, int reg);

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449void sdhci_set_bus_width(struct sdhci_host *host, int width);
450void sdhci_reset(struct sdhci_host *host, u8 mask);
451void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
452
453#ifdef CONFIG_PM
454extern int sdhci_suspend_host(struct sdhci_host *host);
455extern int sdhci_resume_host(struct sdhci_host *host);
456extern void sdhci_enable_irq_wakeups(struct sdhci_host *host);
269struct sdhci_ops {
270#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
271 u32 (*read_l)(struct sdhci_host *host, int reg);
272 u16 (*read_w)(struct sdhci_host *host, int reg);
273 u8 (*read_b)(struct sdhci_host *host, int reg);
274 void (*write_l)(struct sdhci_host *host, u32 val, int reg);
275 void (*write_w)(struct sdhci_host *host, u16 val, int reg);
276 void (*write_b)(struct sdhci_host *host, u8 val, int reg);

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406void sdhci_set_bus_width(struct sdhci_host *host, int width);
407void sdhci_reset(struct sdhci_host *host, u8 mask);
408void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
409
410#ifdef CONFIG_PM
411extern int sdhci_suspend_host(struct sdhci_host *host);
412extern int sdhci_resume_host(struct sdhci_host *host);
413extern void sdhci_enable_irq_wakeups(struct sdhci_host *host);
457#endif
458
459#ifdef CONFIG_PM_RUNTIME
460extern int sdhci_runtime_suspend_host(struct sdhci_host *host);
461extern int sdhci_runtime_resume_host(struct sdhci_host *host);
462#endif
463
464#endif /* __SDHCI_HW_H */
414extern int sdhci_runtime_suspend_host(struct sdhci_host *host);
415extern int sdhci_runtime_resume_host(struct sdhci_host *host);
416#endif
417
418#endif /* __SDHCI_HW_H */