sdhci.c (e9fb05d5bca7428f2749d059559e9657c710fe53) sdhci.c (162d6f98005fce408efc5af73956c434ae08ef73)
1/*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at

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39
40#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
41 defined(CONFIG_MMC_SDHCI_MODULE))
42#define SDHCI_USE_LEDS_CLASS
43#endif
44
45#define MAX_TUNING_LOOP 40
46
1/*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at

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39
40#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
41 defined(CONFIG_MMC_SDHCI_MODULE))
42#define SDHCI_USE_LEDS_CLASS
43#endif
44
45#define MAX_TUNING_LOOP 40
46
47#define ADMA_SIZE ((128 * 2 + 1) * 4)
48
47static unsigned int debug_quirks = 0;
48static unsigned int debug_quirks2;
49
50static void sdhci_finish_data(struct sdhci_host *);
51
52static void sdhci_finish_command(struct sdhci_host *);
53static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
54static void sdhci_tuning_timer(unsigned long data);
55static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
56
49static unsigned int debug_quirks = 0;
50static unsigned int debug_quirks2;
51
52static void sdhci_finish_data(struct sdhci_host *);
53
54static void sdhci_finish_command(struct sdhci_host *);
55static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
56static void sdhci_tuning_timer(unsigned long data);
57static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
58
57#ifdef CONFIG_PM_RUNTIME
59#ifdef CONFIG_PM
58static int sdhci_runtime_pm_get(struct sdhci_host *host);
59static int sdhci_runtime_pm_put(struct sdhci_host *host);
60static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
61static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
62#else
63static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
64{
65 return 0;

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112 sdhci_readl(host, SDHCI_CAPABILITIES),
113 sdhci_readl(host, SDHCI_CAPABILITIES_1));
114 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
115 sdhci_readw(host, SDHCI_COMMAND),
116 sdhci_readl(host, SDHCI_MAX_CURRENT));
117 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
118 sdhci_readw(host, SDHCI_HOST_CONTROL2));
119
60static int sdhci_runtime_pm_get(struct sdhci_host *host);
61static int sdhci_runtime_pm_put(struct sdhci_host *host);
62static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
63static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
64#else
65static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
66{
67 return 0;

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114 sdhci_readl(host, SDHCI_CAPABILITIES),
115 sdhci_readl(host, SDHCI_CAPABILITIES_1));
116 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
117 sdhci_readw(host, SDHCI_COMMAND),
118 sdhci_readl(host, SDHCI_MAX_CURRENT));
119 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
120 sdhci_readw(host, SDHCI_HOST_CONTROL2));
121
120 if (host->flags & SDHCI_USE_ADMA) {
121 if (host->flags & SDHCI_USE_64_BIT_DMA)
122 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
123 readl(host->ioaddr + SDHCI_ADMA_ERROR),
124 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
125 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
126 else
127 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
128 readl(host->ioaddr + SDHCI_ADMA_ERROR),
129 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
130 }
122 if (host->flags & SDHCI_USE_ADMA)
123 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
124 readl(host->ioaddr + SDHCI_ADMA_ERROR),
125 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
131
132 pr_debug(DRIVER_NAME ": ===========================================\n");
133}
134
135/*****************************************************************************\
136 * *
137 * Low level functions *
138 * *

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448}
449
450static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
451{
452 kunmap_atomic(buffer);
453 local_irq_restore(*flags);
454}
455
126
127 pr_debug(DRIVER_NAME ": ===========================================\n");
128}
129
130/*****************************************************************************\
131 * *
132 * Low level functions *
133 * *

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443}
444
445static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
446{
447 kunmap_atomic(buffer);
448 local_irq_restore(*flags);
449}
450
456static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
457 dma_addr_t addr, int len, unsigned cmd)
451static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
458{
452{
459 struct sdhci_adma2_64_desc *dma_desc = desc;
453 __le32 *dataddr = (__le32 __force *)(desc + 4);
454 __le16 *cmdlen = (__le16 __force *)desc;
460
455
461 /* 32-bit and 64-bit descriptors have these members in same position */
462 dma_desc->cmd = cpu_to_le16(cmd);
463 dma_desc->len = cpu_to_le16(len);
464 dma_desc->addr_lo = cpu_to_le32((u32)addr);
456 /* SDHCI specification says ADMA descriptors should be 4 byte
457 * aligned, so using 16 or 32bit operations should be safe. */
465
458
466 if (host->flags & SDHCI_USE_64_BIT_DMA)
467 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
468}
459 cmdlen[0] = cpu_to_le16(cmd);
460 cmdlen[1] = cpu_to_le16(len);
469
461
470static void sdhci_adma_mark_end(void *desc)
471{
472 struct sdhci_adma2_64_desc *dma_desc = desc;
473
474 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
475 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
462 dataddr[0] = cpu_to_le32(addr);
476}
477
478static int sdhci_adma_table_pre(struct sdhci_host *host,
479 struct mmc_data *data)
480{
481 int direction;
482
463}
464
465static int sdhci_adma_table_pre(struct sdhci_host *host,
466 struct mmc_data *data)
467{
468 int direction;
469
483 void *desc;
484 void *align;
470 u8 *desc;
471 u8 *align;
485 dma_addr_t addr;
486 dma_addr_t align_addr;
487 int len, offset;
488
489 struct scatterlist *sg;
490 int i;
491 char *buffer;
492 unsigned long flags;

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497 */
498
499 if (data->flags & MMC_DATA_READ)
500 direction = DMA_FROM_DEVICE;
501 else
502 direction = DMA_TO_DEVICE;
503
504 host->align_addr = dma_map_single(mmc_dev(host->mmc),
472 dma_addr_t addr;
473 dma_addr_t align_addr;
474 int len, offset;
475
476 struct scatterlist *sg;
477 int i;
478 char *buffer;
479 unsigned long flags;

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484 */
485
486 if (data->flags & MMC_DATA_READ)
487 direction = DMA_FROM_DEVICE;
488 else
489 direction = DMA_TO_DEVICE;
490
491 host->align_addr = dma_map_single(mmc_dev(host->mmc),
505 host->align_buffer, host->align_buffer_sz, direction);
492 host->align_buffer, 128 * 4, direction);
506 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
507 goto fail;
493 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
494 goto fail;
508 BUG_ON(host->align_addr & host->align_mask);
495 BUG_ON(host->align_addr & 0x3);
509
510 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
511 data->sg, data->sg_len, direction);
512 if (host->sg_count == 0)
513 goto unmap_align;
514
496
497 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
498 data->sg, data->sg_len, direction);
499 if (host->sg_count == 0)
500 goto unmap_align;
501
515 desc = host->adma_table;
502 desc = host->adma_desc;
516 align = host->align_buffer;
517
518 align_addr = host->align_addr;
519
520 for_each_sg(data->sg, sg, host->sg_count, i) {
521 addr = sg_dma_address(sg);
522 len = sg_dma_len(sg);
523
524 /*
525 * The SDHCI specification states that ADMA
526 * addresses must be 32-bit aligned. If they
527 * aren't, then we use a bounce buffer for
528 * the (up to three) bytes that screw up the
529 * alignment.
530 */
503 align = host->align_buffer;
504
505 align_addr = host->align_addr;
506
507 for_each_sg(data->sg, sg, host->sg_count, i) {
508 addr = sg_dma_address(sg);
509 len = sg_dma_len(sg);
510
511 /*
512 * The SDHCI specification states that ADMA
513 * addresses must be 32-bit aligned. If they
514 * aren't, then we use a bounce buffer for
515 * the (up to three) bytes that screw up the
516 * alignment.
517 */
531 offset = (host->align_sz - (addr & host->align_mask)) &
532 host->align_mask;
518 offset = (4 - (addr & 0x3)) & 0x3;
533 if (offset) {
534 if (data->flags & MMC_DATA_WRITE) {
535 buffer = sdhci_kmap_atomic(sg, &flags);
519 if (offset) {
520 if (data->flags & MMC_DATA_WRITE) {
521 buffer = sdhci_kmap_atomic(sg, &flags);
536 WARN_ON(((long)buffer & (PAGE_SIZE - 1)) >
537 (PAGE_SIZE - offset));
522 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
538 memcpy(align, buffer, offset);
539 sdhci_kunmap_atomic(buffer, &flags);
540 }
541
542 /* tran, valid */
523 memcpy(align, buffer, offset);
524 sdhci_kunmap_atomic(buffer, &flags);
525 }
526
527 /* tran, valid */
543 sdhci_adma_write_desc(host, desc, align_addr, offset,
544 ADMA2_TRAN_VALID);
528 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
545
546 BUG_ON(offset > 65536);
547
529
530 BUG_ON(offset > 65536);
531
548 align += host->align_sz;
549 align_addr += host->align_sz;
532 align += 4;
533 align_addr += 4;
550
534
551 desc += host->desc_sz;
535 desc += 8;
552
553 addr += offset;
554 len -= offset;
555 }
556
557 BUG_ON(len > 65536);
558
559 /* tran, valid */
536
537 addr += offset;
538 len -= offset;
539 }
540
541 BUG_ON(len > 65536);
542
543 /* tran, valid */
560 sdhci_adma_write_desc(host, desc, addr, len, ADMA2_TRAN_VALID);
561 desc += host->desc_sz;
544 sdhci_set_adma_desc(desc, addr, len, 0x21);
545 desc += 8;
562
563 /*
564 * If this triggers then we have a calculation bug
565 * somewhere. :/
566 */
546
547 /*
548 * If this triggers then we have a calculation bug
549 * somewhere. :/
550 */
567 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
551 WARN_ON((desc - host->adma_desc) > ADMA_SIZE);
568 }
569
570 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
571 /*
572 * Mark the last descriptor as the terminating descriptor
573 */
552 }
553
554 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
555 /*
556 * Mark the last descriptor as the terminating descriptor
557 */
574 if (desc != host->adma_table) {
575 desc -= host->desc_sz;
576 sdhci_adma_mark_end(desc);
558 if (desc != host->adma_desc) {
559 desc -= 8;
560 desc[0] |= 0x2; /* end */
577 }
578 } else {
579 /*
580 * Add a terminating entry.
581 */
582
583 /* nop, end, valid */
561 }
562 } else {
563 /*
564 * Add a terminating entry.
565 */
566
567 /* nop, end, valid */
584 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
568 sdhci_set_adma_desc(desc, 0, 0, 0x3);
585 }
586
587 /*
588 * Resync align buffer as we might have changed it.
589 */
590 if (data->flags & MMC_DATA_WRITE) {
591 dma_sync_single_for_device(mmc_dev(host->mmc),
569 }
570
571 /*
572 * Resync align buffer as we might have changed it.
573 */
574 if (data->flags & MMC_DATA_WRITE) {
575 dma_sync_single_for_device(mmc_dev(host->mmc),
592 host->align_addr, host->align_buffer_sz, direction);
576 host->align_addr, 128 * 4, direction);
593 }
594
595 return 0;
596
597unmap_align:
598 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
577 }
578
579 return 0;
580
581unmap_align:
582 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
599 host->align_buffer_sz, direction);
583 128 * 4, direction);
600fail:
601 return -EINVAL;
602}
603
604static void sdhci_adma_table_post(struct sdhci_host *host,
605 struct mmc_data *data)
606{
607 int direction;
608
609 struct scatterlist *sg;
610 int i, size;
584fail:
585 return -EINVAL;
586}
587
588static void sdhci_adma_table_post(struct sdhci_host *host,
589 struct mmc_data *data)
590{
591 int direction;
592
593 struct scatterlist *sg;
594 int i, size;
611 void *align;
595 u8 *align;
612 char *buffer;
613 unsigned long flags;
614 bool has_unaligned;
615
616 if (data->flags & MMC_DATA_READ)
617 direction = DMA_FROM_DEVICE;
618 else
619 direction = DMA_TO_DEVICE;
620
621 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
596 char *buffer;
597 unsigned long flags;
598 bool has_unaligned;
599
600 if (data->flags & MMC_DATA_READ)
601 direction = DMA_FROM_DEVICE;
602 else
603 direction = DMA_TO_DEVICE;
604
605 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
622 host->align_buffer_sz, direction);
606 128 * 4, direction);
623
624 /* Do a quick scan of the SG list for any unaligned mappings */
625 has_unaligned = false;
626 for_each_sg(data->sg, sg, host->sg_count, i)
607
608 /* Do a quick scan of the SG list for any unaligned mappings */
609 has_unaligned = false;
610 for_each_sg(data->sg, sg, host->sg_count, i)
627 if (sg_dma_address(sg) & host->align_mask) {
611 if (sg_dma_address(sg) & 3) {
628 has_unaligned = true;
629 break;
630 }
631
632 if (has_unaligned && data->flags & MMC_DATA_READ) {
633 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
634 data->sg_len, direction);
635
636 align = host->align_buffer;
637
638 for_each_sg(data->sg, sg, host->sg_count, i) {
612 has_unaligned = true;
613 break;
614 }
615
616 if (has_unaligned && data->flags & MMC_DATA_READ) {
617 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
618 data->sg_len, direction);
619
620 align = host->align_buffer;
621
622 for_each_sg(data->sg, sg, host->sg_count, i) {
639 if (sg_dma_address(sg) & host->align_mask) {
640 size = host->align_sz -
641 (sg_dma_address(sg) & host->align_mask);
623 if (sg_dma_address(sg) & 0x3) {
624 size = 4 - (sg_dma_address(sg) & 0x3);
642
643 buffer = sdhci_kmap_atomic(sg, &flags);
625
626 buffer = sdhci_kmap_atomic(sg, &flags);
644 WARN_ON(((long)buffer & (PAGE_SIZE - 1)) >
645 (PAGE_SIZE - size));
627 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
646 memcpy(buffer, align, size);
647 sdhci_kunmap_atomic(buffer, &flags);
648
628 memcpy(buffer, align, size);
629 sdhci_kunmap_atomic(buffer, &flags);
630
649 align += host->align_sz;
631 align += 4;
650 }
651 }
652 }
653
654 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
655 data->sg_len, direction);
656}
657

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835 * This only happens when someone fed
836 * us an invalid request.
837 */
838 WARN_ON(1);
839 host->flags &= ~SDHCI_REQ_USE_DMA;
840 } else {
841 sdhci_writel(host, host->adma_addr,
842 SDHCI_ADMA_ADDRESS);
632 }
633 }
634 }
635
636 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
637 data->sg_len, direction);
638}
639

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817 * This only happens when someone fed
818 * us an invalid request.
819 */
820 WARN_ON(1);
821 host->flags &= ~SDHCI_REQ_USE_DMA;
822 } else {
823 sdhci_writel(host, host->adma_addr,
824 SDHCI_ADMA_ADDRESS);
843 if (host->flags & SDHCI_USE_64_BIT_DMA)
844 sdhci_writel(host,
845 (u64)host->adma_addr >> 32,
846 SDHCI_ADMA_ADDRESS_HI);
847 }
848 } else {
849 int sg_cnt;
850
851 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
852 data->sg, data->sg_len,
853 (data->flags & MMC_DATA_READ) ?
854 DMA_FROM_DEVICE :

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872 * Always adjust the DMA selection as some controllers
873 * (e.g. JMicron) can't do PIO properly when the selection
874 * is ADMA.
875 */
876 if (host->version >= SDHCI_SPEC_200) {
877 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
878 ctrl &= ~SDHCI_CTRL_DMA_MASK;
879 if ((host->flags & SDHCI_REQ_USE_DMA) &&
825 }
826 } else {
827 int sg_cnt;
828
829 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
830 data->sg, data->sg_len,
831 (data->flags & MMC_DATA_READ) ?
832 DMA_FROM_DEVICE :

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850 * Always adjust the DMA selection as some controllers
851 * (e.g. JMicron) can't do PIO properly when the selection
852 * is ADMA.
853 */
854 if (host->version >= SDHCI_SPEC_200) {
855 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
856 ctrl &= ~SDHCI_CTRL_DMA_MASK;
857 if ((host->flags & SDHCI_REQ_USE_DMA) &&
880 (host->flags & SDHCI_USE_ADMA)) {
881 if (host->flags & SDHCI_USE_64_BIT_DMA)
882 ctrl |= SDHCI_CTRL_ADMA64;
883 else
884 ctrl |= SDHCI_CTRL_ADMA32;
885 } else {
858 (host->flags & SDHCI_USE_ADMA))
859 ctrl |= SDHCI_CTRL_ADMA32;
860 else
886 ctrl |= SDHCI_CTRL_SDMA;
861 ctrl |= SDHCI_CTRL_SDMA;
887 }
888 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
889 }
890
891 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
892 int flags;
893
894 flags = SG_MITER_ATOMIC;
895 if (host->data->flags & MMC_DATA_READ)

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910
911static void sdhci_set_transfer_mode(struct sdhci_host *host,
912 struct mmc_command *cmd)
913{
914 u16 mode;
915 struct mmc_data *data = cmd->data;
916
917 if (data == NULL) {
862 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
863 }
864
865 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
866 int flags;
867
868 flags = SG_MITER_ATOMIC;
869 if (host->data->flags & MMC_DATA_READ)

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884
885static void sdhci_set_transfer_mode(struct sdhci_host *host,
886 struct mmc_command *cmd)
887{
888 u16 mode;
889 struct mmc_data *data = cmd->data;
890
891 if (data == NULL) {
918 if (host->quirks2 &
919 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
920 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
921 } else {
922 /* clear Auto CMD settings for no data CMDs */
892 /* clear Auto CMD settings for no data CMDs */
923 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
924 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
893 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
894 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
925 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
895 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
926 }
927 return;
928 }
929
930 WARN_ON(!host->data);
931
932 mode = SDHCI_TRNS_BLK_CNT_EN;
933 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
934 mode |= SDHCI_TRNS_MULTI;

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1143 break;
1144 case MMC_TIMING_UHS_SDR104:
1145 case MMC_TIMING_MMC_HS200:
1146 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1147 break;
1148 case MMC_TIMING_UHS_DDR50:
1149 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1150 break;
896 return;
897 }
898
899 WARN_ON(!host->data);
900
901 mode = SDHCI_TRNS_BLK_CNT_EN;
902 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
903 mode |= SDHCI_TRNS_MULTI;

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1112 break;
1113 case MMC_TIMING_UHS_SDR104:
1114 case MMC_TIMING_MMC_HS200:
1115 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1116 break;
1117 case MMC_TIMING_UHS_DDR50:
1118 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1119 break;
1151 case MMC_TIMING_MMC_HS400:
1152 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1153 break;
1154 default:
1155 pr_warn("%s: Invalid UHS-I mode selected\n",
1156 mmc_hostname(host->mmc));
1157 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1158 break;
1159 }
1160 return preset;
1161}

--- 311 unchanged lines hidden (view full) ---

1473 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1474 else if (timing == MMC_TIMING_UHS_SDR25)
1475 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1476 else if (timing == MMC_TIMING_UHS_SDR50)
1477 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1478 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1479 (timing == MMC_TIMING_MMC_DDR52))
1480 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1120 default:
1121 pr_warn("%s: Invalid UHS-I mode selected\n",
1122 mmc_hostname(host->mmc));
1123 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1124 break;
1125 }
1126 return preset;
1127}

--- 311 unchanged lines hidden (view full) ---

1439 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1440 else if (timing == MMC_TIMING_UHS_SDR25)
1441 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1442 else if (timing == MMC_TIMING_UHS_SDR50)
1443 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1444 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1445 (timing == MMC_TIMING_MMC_DDR52))
1446 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1481 else if (timing == MMC_TIMING_MMC_HS400)
1482 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1483 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1484}
1485EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1486
1487static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1488{
1489 unsigned long flags;
1490 u8 ctrl;

--- 55 unchanged lines hidden (view full) ---

1546 ctrl |= SDHCI_CTRL_HISPD;
1547 else
1548 ctrl &= ~SDHCI_CTRL_HISPD;
1549
1550 if (host->version >= SDHCI_SPEC_300) {
1551 u16 clk, ctrl_2;
1552
1553 /* In case of UHS-I modes, set High Speed Enable */
1447 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1448}
1449EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1450
1451static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1452{
1453 unsigned long flags;
1454 u8 ctrl;

--- 55 unchanged lines hidden (view full) ---

1510 ctrl |= SDHCI_CTRL_HISPD;
1511 else
1512 ctrl &= ~SDHCI_CTRL_HISPD;
1513
1514 if (host->version >= SDHCI_SPEC_300) {
1515 u16 clk, ctrl_2;
1516
1517 /* In case of UHS-I modes, set High Speed Enable */
1554 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1555 (ios->timing == MMC_TIMING_MMC_HS200) ||
1518 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1556 (ios->timing == MMC_TIMING_MMC_DDR52) ||
1557 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1558 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1559 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1560 (ios->timing == MMC_TIMING_UHS_SDR25))
1561 ctrl |= SDHCI_CTRL_HISPD;
1562
1563 if (!host->preset_enabled) {

--- 330 unchanged lines hidden (view full) ---

1894 /*
1895 * The Host Controller needs tuning only in case of SDR104 mode
1896 * and for SDR50 mode when Use Tuning for SDR50 is set in the
1897 * Capabilities register.
1898 * If the Host Controller supports the HS200 mode then the
1899 * tuning function has to be executed.
1900 */
1901 switch (host->timing) {
1519 (ios->timing == MMC_TIMING_MMC_DDR52) ||
1520 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1521 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1522 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1523 (ios->timing == MMC_TIMING_UHS_SDR25))
1524 ctrl |= SDHCI_CTRL_HISPD;
1525
1526 if (!host->preset_enabled) {

--- 330 unchanged lines hidden (view full) ---

1857 /*
1858 * The Host Controller needs tuning only in case of SDR104 mode
1859 * and for SDR50 mode when Use Tuning for SDR50 is set in the
1860 * Capabilities register.
1861 * If the Host Controller supports the HS200 mode then the
1862 * tuning function has to be executed.
1863 */
1864 switch (host->timing) {
1902 case MMC_TIMING_MMC_HS400:
1903 case MMC_TIMING_MMC_HS200:
1904 case MMC_TIMING_UHS_SDR104:
1905 break;
1906
1907 case MMC_TIMING_UHS_SDR50:
1908 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1909 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1910 break;

--- 266 unchanged lines hidden (view full) ---

2177 mrq = host->mrq;
2178
2179 /*
2180 * The controller needs a reset of internal state machines
2181 * upon error conditions.
2182 */
2183 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2184 ((mrq->cmd && mrq->cmd->error) ||
1865 case MMC_TIMING_MMC_HS200:
1866 case MMC_TIMING_UHS_SDR104:
1867 break;
1868
1869 case MMC_TIMING_UHS_SDR50:
1870 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1871 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1872 break;

--- 266 unchanged lines hidden (view full) ---

2139 mrq = host->mrq;
2140
2141 /*
2142 * The controller needs a reset of internal state machines
2143 * upon error conditions.
2144 */
2145 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2146 ((mrq->cmd && mrq->cmd->error) ||
2185 (mrq->sbc && mrq->sbc->error) ||
2186 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2187 (mrq->data->stop && mrq->data->stop->error))) ||
2188 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2147 (mrq->data && (mrq->data->error ||
2148 (mrq->data->stop && mrq->data->stop->error))) ||
2149 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2189
2190 /* Some controllers need this kick or reset won't work here */
2191 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2192 /* This is to force an update */
2193 host->ops->set_clock(host, host->clock);
2194
2195 /* Spec says we should do both at the same time, but Ricoh
2196 controllers do not like that. */

--- 119 unchanged lines hidden (view full) ---

2316 *mask &= ~SDHCI_INT_DATA_END;
2317 }
2318
2319 if (intmask & SDHCI_INT_RESPONSE)
2320 sdhci_finish_command(host);
2321}
2322
2323#ifdef CONFIG_MMC_DEBUG
2150
2151 /* Some controllers need this kick or reset won't work here */
2152 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2153 /* This is to force an update */
2154 host->ops->set_clock(host, host->clock);
2155
2156 /* Spec says we should do both at the same time, but Ricoh
2157 controllers do not like that. */

--- 119 unchanged lines hidden (view full) ---

2277 *mask &= ~SDHCI_INT_DATA_END;
2278 }
2279
2280 if (intmask & SDHCI_INT_RESPONSE)
2281 sdhci_finish_command(host);
2282}
2283
2284#ifdef CONFIG_MMC_DEBUG
2324static void sdhci_adma_show_error(struct sdhci_host *host)
2285static void sdhci_show_adma_error(struct sdhci_host *host)
2325{
2326 const char *name = mmc_hostname(host->mmc);
2286{
2287 const char *name = mmc_hostname(host->mmc);
2327 void *desc = host->adma_table;
2288 u8 *desc = host->adma_desc;
2289 __le32 *dma;
2290 __le16 *len;
2291 u8 attr;
2328
2329 sdhci_dumpregs(host);
2330
2331 while (true) {
2292
2293 sdhci_dumpregs(host);
2294
2295 while (true) {
2332 struct sdhci_adma2_64_desc *dma_desc = desc;
2296 dma = (__le32 *)(desc + 4);
2297 len = (__le16 *)(desc + 2);
2298 attr = *desc;
2333
2299
2334 if (host->flags & SDHCI_USE_64_BIT_DMA)
2335 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2336 name, desc, le32_to_cpu(dma_desc->addr_hi),
2337 le32_to_cpu(dma_desc->addr_lo),
2338 le16_to_cpu(dma_desc->len),
2339 le16_to_cpu(dma_desc->cmd));
2340 else
2341 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2342 name, desc, le32_to_cpu(dma_desc->addr_lo),
2343 le16_to_cpu(dma_desc->len),
2344 le16_to_cpu(dma_desc->cmd));
2300 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2301 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2345
2302
2346 desc += host->desc_sz;
2303 desc += 8;
2347
2304
2348 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2305 if (attr & 2)
2349 break;
2350 }
2351}
2352#else
2306 break;
2307 }
2308}
2309#else
2353static void sdhci_adma_show_error(struct sdhci_host *host) { }
2310static void sdhci_show_adma_error(struct sdhci_host *host) { }
2354#endif
2355
2356static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2357{
2358 u32 command;
2359 BUG_ON(intmask == 0);
2360
2361 /* CMD19 generates _only_ Buffer Read Ready interrupt */

--- 46 unchanged lines hidden (view full) ---

2408 else if (intmask & SDHCI_INT_DATA_END_BIT)
2409 host->data->error = -EILSEQ;
2410 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2411 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2412 != MMC_BUS_TEST_R)
2413 host->data->error = -EILSEQ;
2414 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2415 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2311#endif
2312
2313static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2314{
2315 u32 command;
2316 BUG_ON(intmask == 0);
2317
2318 /* CMD19 generates _only_ Buffer Read Ready interrupt */

--- 46 unchanged lines hidden (view full) ---

2365 else if (intmask & SDHCI_INT_DATA_END_BIT)
2366 host->data->error = -EILSEQ;
2367 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2368 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2369 != MMC_BUS_TEST_R)
2370 host->data->error = -EILSEQ;
2371 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2372 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2416 sdhci_adma_show_error(host);
2373 sdhci_show_adma_error(host);
2417 host->data->error = -EIO;
2418 if (host->ops->adma_workaround)
2419 host->ops->adma_workaround(host, intmask);
2420 }
2421
2422 if (host->data->error)
2423 sdhci_finish_data(host);
2424 else {

--- 267 unchanged lines hidden (view full) ---

2692 /* Set the re-tuning expiration flag */
2693 if (host->flags & SDHCI_USING_RETUNING_TIMER)
2694 host->flags |= SDHCI_NEEDS_RETUNING;
2695
2696 return ret;
2697}
2698
2699EXPORT_SYMBOL_GPL(sdhci_resume_host);
2374 host->data->error = -EIO;
2375 if (host->ops->adma_workaround)
2376 host->ops->adma_workaround(host, intmask);
2377 }
2378
2379 if (host->data->error)
2380 sdhci_finish_data(host);
2381 else {

--- 267 unchanged lines hidden (view full) ---

2649 /* Set the re-tuning expiration flag */
2650 if (host->flags & SDHCI_USING_RETUNING_TIMER)
2651 host->flags |= SDHCI_NEEDS_RETUNING;
2652
2653 return ret;
2654}
2655
2656EXPORT_SYMBOL_GPL(sdhci_resume_host);
2700#endif /* CONFIG_PM */
2701
2657
2702#ifdef CONFIG_PM_RUNTIME
2703
2704static int sdhci_runtime_pm_get(struct sdhci_host *host)
2705{
2706 return pm_runtime_get_sync(host->mmc->parent);
2707}
2708
2709static int sdhci_runtime_pm_put(struct sdhci_host *host)
2710{
2711 pm_runtime_mark_last_busy(host->mmc->parent);

--- 83 unchanged lines hidden (view full) ---

2795 sdhci_enable_card_detection(host);
2796
2797 spin_unlock_irqrestore(&host->lock, flags);
2798
2799 return 0;
2800}
2801EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2802
2658static int sdhci_runtime_pm_get(struct sdhci_host *host)
2659{
2660 return pm_runtime_get_sync(host->mmc->parent);
2661}
2662
2663static int sdhci_runtime_pm_put(struct sdhci_host *host)
2664{
2665 pm_runtime_mark_last_busy(host->mmc->parent);

--- 83 unchanged lines hidden (view full) ---

2749 sdhci_enable_card_detection(host);
2750
2751 spin_unlock_irqrestore(&host->lock, flags);
2752
2753 return 0;
2754}
2755EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2756
2803#endif
2757#endif /* CONFIG_PM */
2804
2805/*****************************************************************************\
2806 * *
2807 * Device allocation/registration *
2808 * *
2809\*****************************************************************************/
2810
2811struct sdhci_host *sdhci_alloc_host(struct device *dev,

--- 75 unchanged lines hidden (view full) ---

2887 host->flags |= SDHCI_USE_ADMA;
2888
2889 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2890 (host->flags & SDHCI_USE_ADMA)) {
2891 DBG("Disabling ADMA as it is marked broken\n");
2892 host->flags &= ~SDHCI_USE_ADMA;
2893 }
2894
2758
2759/*****************************************************************************\
2760 * *
2761 * Device allocation/registration *
2762 * *
2763\*****************************************************************************/
2764
2765struct sdhci_host *sdhci_alloc_host(struct device *dev,

--- 75 unchanged lines hidden (view full) ---

2841 host->flags |= SDHCI_USE_ADMA;
2842
2843 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2844 (host->flags & SDHCI_USE_ADMA)) {
2845 DBG("Disabling ADMA as it is marked broken\n");
2846 host->flags &= ~SDHCI_USE_ADMA;
2847 }
2848
2895 /*
2896 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2897 * and *must* do 64-bit DMA. A driver has the opportunity to change
2898 * that during the first call to ->enable_dma(). Similarly
2899 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2900 * implement.
2901 */
2902 if (sdhci_readl(host, SDHCI_CAPABILITIES) & SDHCI_CAN_64BIT)
2903 host->flags |= SDHCI_USE_64_BIT_DMA;
2904
2905 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2906 if (host->ops->enable_dma) {
2907 if (host->ops->enable_dma(host)) {
2908 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
2909 mmc_hostname(mmc));
2910 host->flags &=
2911 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2912 }
2913 }
2914 }
2915
2849 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2850 if (host->ops->enable_dma) {
2851 if (host->ops->enable_dma(host)) {
2852 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
2853 mmc_hostname(mmc));
2854 host->flags &=
2855 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2856 }
2857 }
2858 }
2859
2916 /* SDMA does not support 64-bit DMA */
2917 if (host->flags & SDHCI_USE_64_BIT_DMA)
2918 host->flags &= ~SDHCI_USE_SDMA;
2919
2920 if (host->flags & SDHCI_USE_ADMA) {
2921 /*
2860 if (host->flags & SDHCI_USE_ADMA) {
2861 /*
2922 * The DMA descriptor table size is calculated as the maximum
2923 * number of segments times 2, to allow for an alignment
2924 * descriptor for each segment, plus 1 for a nop end descriptor,
2925 * all multipled by the descriptor size.
2862 * We need to allocate descriptors for all sg entries
2863 * (128) and potentially one alignment transfer for
2864 * each of those entries.
2926 */
2865 */
2927 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2928 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2929 SDHCI_ADMA2_64_DESC_SZ;
2930 host->align_buffer_sz = SDHCI_MAX_SEGS *
2931 SDHCI_ADMA2_64_ALIGN;
2932 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
2933 host->align_sz = SDHCI_ADMA2_64_ALIGN;
2934 host->align_mask = SDHCI_ADMA2_64_ALIGN - 1;
2935 } else {
2936 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2937 SDHCI_ADMA2_32_DESC_SZ;
2938 host->align_buffer_sz = SDHCI_MAX_SEGS *
2939 SDHCI_ADMA2_32_ALIGN;
2940 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
2941 host->align_sz = SDHCI_ADMA2_32_ALIGN;
2942 host->align_mask = SDHCI_ADMA2_32_ALIGN - 1;
2943 }
2944 host->adma_table = dma_alloc_coherent(mmc_dev(mmc),
2945 host->adma_table_sz,
2946 &host->adma_addr,
2947 GFP_KERNEL);
2948 host->align_buffer = kmalloc(host->align_buffer_sz, GFP_KERNEL);
2949 if (!host->adma_table || !host->align_buffer) {
2950 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
2951 host->adma_table, host->adma_addr);
2866 host->adma_desc = dma_alloc_coherent(mmc_dev(mmc),
2867 ADMA_SIZE, &host->adma_addr,
2868 GFP_KERNEL);
2869 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2870 if (!host->adma_desc || !host->align_buffer) {
2871 dma_free_coherent(mmc_dev(mmc), ADMA_SIZE,
2872 host->adma_desc, host->adma_addr);
2952 kfree(host->align_buffer);
2953 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2954 mmc_hostname(mmc));
2955 host->flags &= ~SDHCI_USE_ADMA;
2873 kfree(host->align_buffer);
2874 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2875 mmc_hostname(mmc));
2876 host->flags &= ~SDHCI_USE_ADMA;
2956 host->adma_table = NULL;
2877 host->adma_desc = NULL;
2957 host->align_buffer = NULL;
2878 host->align_buffer = NULL;
2958 } else if (host->adma_addr & host->align_mask) {
2879 } else if (host->adma_addr & 3) {
2959 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
2960 mmc_hostname(mmc));
2961 host->flags &= ~SDHCI_USE_ADMA;
2880 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
2881 mmc_hostname(mmc));
2882 host->flags &= ~SDHCI_USE_ADMA;
2962 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
2963 host->adma_table, host->adma_addr);
2883 dma_free_coherent(mmc_dev(mmc), ADMA_SIZE,
2884 host->adma_desc, host->adma_addr);
2964 kfree(host->align_buffer);
2885 kfree(host->align_buffer);
2965 host->adma_table = NULL;
2886 host->adma_desc = NULL;
2966 host->align_buffer = NULL;
2967 }
2968 }
2969
2970 /*
2971 * If we use DMA, then it's up to the caller to set the DMA
2972 * mask, but PIO does not need the hw shim so we set a new
2973 * mask here in that case.

--- 124 unchanged lines hidden (view full) ---

3098 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3099 1950000))
3100 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3101 SDHCI_SUPPORT_SDR50 |
3102 SDHCI_SUPPORT_DDR50);
3103 if (ret) {
3104 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3105 mmc_hostname(mmc), ret);
2887 host->align_buffer = NULL;
2888 }
2889 }
2890
2891 /*
2892 * If we use DMA, then it's up to the caller to set the DMA
2893 * mask, but PIO does not need the hw shim so we set a new
2894 * mask here in that case.

--- 124 unchanged lines hidden (view full) ---

3019 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3020 1950000))
3021 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3022 SDHCI_SUPPORT_SDR50 |
3023 SDHCI_SUPPORT_DDR50);
3024 if (ret) {
3025 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3026 mmc_hostname(mmc), ret);
3106 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3027 mmc->supply.vqmmc = NULL;
3107 }
3108 }
3109
3110 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3111 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3112 SDHCI_SUPPORT_DDR50);
3113
3114 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3115 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3116 SDHCI_SUPPORT_DDR50))
3117 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3118
3119 /* SDR104 supports also implies SDR50 support */
3120 if (caps[1] & SDHCI_SUPPORT_SDR104) {
3121 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3122 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3123 * field can be promoted to support HS200.
3124 */
3028 }
3029 }
3030
3031 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3032 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3033 SDHCI_SUPPORT_DDR50);
3034
3035 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3036 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3037 SDHCI_SUPPORT_DDR50))
3038 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3039
3040 /* SDR104 supports also implies SDR50 support */
3041 if (caps[1] & SDHCI_SUPPORT_SDR104) {
3042 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3043 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3044 * field can be promoted to support HS200.
3045 */
3125 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3046 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200)) {
3126 mmc->caps2 |= MMC_CAP2_HS200;
3047 mmc->caps2 |= MMC_CAP2_HS200;
3048 if (IS_ERR(mmc->supply.vqmmc) ||
3049 !regulator_is_supported_voltage
3050 (mmc->supply.vqmmc, 1100000, 1300000))
3051 mmc->caps2 &= ~MMC_CAP2_HS200_1_2V_SDR;
3052 }
3127 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3128 mmc->caps |= MMC_CAP_UHS_SDR50;
3129
3053 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3054 mmc->caps |= MMC_CAP_UHS_SDR50;
3055
3130 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3131 (caps[1] & SDHCI_SUPPORT_HS400))
3132 mmc->caps2 |= MMC_CAP2_HS400;
3133
3134 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3135 (IS_ERR(mmc->supply.vqmmc) ||
3136 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3137 1300000)))
3138 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3139
3140 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3141 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3142 mmc->caps |= MMC_CAP_UHS_DDR50;
3143
3144 /* Does the host need tuning for SDR50? */
3145 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3146 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3147

--- 103 unchanged lines hidden (view full) ---

3251
3252 spin_lock_init(&host->lock);
3253
3254 /*
3255 * Maximum number of segments. Depends on if the hardware
3256 * can do scatter/gather or not.
3257 */
3258 if (host->flags & SDHCI_USE_ADMA)
3056 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3057 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3058 mmc->caps |= MMC_CAP_UHS_DDR50;
3059
3060 /* Does the host need tuning for SDR50? */
3061 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3062 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3063

--- 103 unchanged lines hidden (view full) ---

3167
3168 spin_lock_init(&host->lock);
3169
3170 /*
3171 * Maximum number of segments. Depends on if the hardware
3172 * can do scatter/gather or not.
3173 */
3174 if (host->flags & SDHCI_USE_ADMA)
3259 mmc->max_segs = SDHCI_MAX_SEGS;
3175 mmc->max_segs = 128;
3260 else if (host->flags & SDHCI_USE_SDMA)
3261 mmc->max_segs = 1;
3262 else /* PIO */
3176 else if (host->flags & SDHCI_USE_SDMA)
3177 mmc->max_segs = 1;
3178 else /* PIO */
3263 mmc->max_segs = SDHCI_MAX_SEGS;
3179 mmc->max_segs = 128;
3264
3265 /*
3266 * Maximum number of sectors in one transfer. Limited by DMA boundary
3267 * size (512KiB).
3268 */
3269 mmc->max_req_size = 524288;
3270
3271 /*

--- 81 unchanged lines hidden (view full) ---

3353#endif
3354
3355 mmiowb();
3356
3357 mmc_add_host(mmc);
3358
3359 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3360 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3180
3181 /*
3182 * Maximum number of sectors in one transfer. Limited by DMA boundary
3183 * size (512KiB).
3184 */
3185 mmc->max_req_size = 524288;
3186
3187 /*

--- 81 unchanged lines hidden (view full) ---

3269#endif
3270
3271 mmiowb();
3272
3273 mmc_add_host(mmc);
3274
3275 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3276 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3361 (host->flags & SDHCI_USE_ADMA) ?
3362 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
3277 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3363 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3364
3365 sdhci_enable_card_detection(host);
3366
3367 return 0;
3368
3369#ifdef SDHCI_USE_LEDS_CLASS
3370reset:

--- 45 unchanged lines hidden (view full) ---

3416 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3417 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3418 free_irq(host->irq, host);
3419
3420 del_timer_sync(&host->timer);
3421
3422 tasklet_kill(&host->finish_tasklet);
3423
3278 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3279
3280 sdhci_enable_card_detection(host);
3281
3282 return 0;
3283
3284#ifdef SDHCI_USE_LEDS_CLASS
3285reset:

--- 45 unchanged lines hidden (view full) ---

3331 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3332 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3333 free_irq(host->irq, host);
3334
3335 del_timer_sync(&host->timer);
3336
3337 tasklet_kill(&host->finish_tasklet);
3338
3339 if (!IS_ERR(mmc->supply.vmmc))
3340 regulator_disable(mmc->supply.vmmc);
3341
3424 if (!IS_ERR(mmc->supply.vqmmc))
3425 regulator_disable(mmc->supply.vqmmc);
3426
3342 if (!IS_ERR(mmc->supply.vqmmc))
3343 regulator_disable(mmc->supply.vqmmc);
3344
3427 if (host->adma_table)
3428 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3429 host->adma_table, host->adma_addr);
3345 if (host->adma_desc)
3346 dma_free_coherent(mmc_dev(mmc), ADMA_SIZE,
3347 host->adma_desc, host->adma_addr);
3430 kfree(host->align_buffer);
3431
3348 kfree(host->align_buffer);
3349
3432 host->adma_table = NULL;
3350 host->adma_desc = NULL;
3433 host->align_buffer = NULL;
3434}
3435
3436EXPORT_SYMBOL_GPL(sdhci_remove_host);
3437
3438void sdhci_free_host(struct sdhci_host *host)
3439{
3440 mmc_free_host(host->mmc);

--- 35 unchanged lines hidden --- 		3351 host->align_buffer = NULL;
3352}
3353
3354EXPORT_SYMBOL_GPL(sdhci_remove_host);
3355
3356void sdhci_free_host(struct sdhci_host *host)
3357{
3358 mmc_free_host(host->mmc);

--- 35 unchanged lines hidden ---