sdhci.c (db985cbd67c45f875ef43cb5febfaa8cbd203c27) sdhci.c (6606110d89aefcb21b9e70adfe064987cbd8393a)
1/*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at

--- 693 unchanged lines hidden (view full) ---

702 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
703 else
704 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
705
706 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
707 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
708}
709
1/*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at

--- 693 unchanged lines hidden (view full) ---

702 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
703 else
704 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
705
706 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
707 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
708}
709
710static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
710static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
711{
712 u8 count;
711{
712 u8 count;
713
714 if (host->ops->set_timeout) {
715 host->ops->set_timeout(host, cmd);
716 } else {
717 count = sdhci_calc_timeout(host, cmd);
718 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
719 }
720}
721
722static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
723{
713 u8 ctrl;
714 struct mmc_data *data = cmd->data;
715 int ret;
716
717 WARN_ON(host->data);
718
724 u8 ctrl;
725 struct mmc_data *data = cmd->data;
726 int ret;
727
728 WARN_ON(host->data);
729
719 if (data || (cmd->flags & MMC_RSP_BUSY)) {
720 count = sdhci_calc_timeout(host, cmd);
721 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
722 }
730 if (data || (cmd->flags & MMC_RSP_BUSY))
731 sdhci_set_timeout(host, cmd);
723
724 if (!data)
725 return;
726
727 /* Sanity checks */
728 BUG_ON(data->blksz * data->blocks > 524288);
729 BUG_ON(data->blksz > host->mmc->max_blk_size);
730 BUG_ON(data->blocks > 65535);

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1002 timeout = jiffies;
1003 if (!cmd->data && cmd->busy_timeout > 9000)
1004 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1005 else
1006 timeout += 10 * HZ;
1007 mod_timer(&host->timer, timeout);
1008
1009 host->cmd = cmd;
732
733 if (!data)
734 return;
735
736 /* Sanity checks */
737 BUG_ON(data->blksz * data->blocks > 524288);
738 BUG_ON(data->blksz > host->mmc->max_blk_size);
739 BUG_ON(data->blocks > 65535);

--- 271 unchanged lines hidden (view full) ---

1011 timeout = jiffies;
1012 if (!cmd->data && cmd->busy_timeout > 9000)
1013 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1014 else
1015 timeout += 10 * HZ;
1016 mod_timer(&host->timer, timeout);
1017
1018 host->cmd = cmd;
1019 host->busy_handle = 0;
1010
1011 sdhci_prepare_data(host, cmd);
1012
1013 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1014
1015 sdhci_set_transfer_mode(host, cmd);
1016
1017 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {

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1189 }
1190 real_div = div;
1191 div >>= 1;
1192 }
1193
1194clock_set:
1195 if (real_div)
1196 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1020
1021 sdhci_prepare_data(host, cmd);
1022
1023 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1024
1025 sdhci_set_transfer_mode(host, cmd);
1026
1027 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {

--- 171 unchanged lines hidden (view full) ---

1199 }
1200 real_div = div;
1201 div >>= 1;
1202 }
1203
1204clock_set:
1205 if (real_div)
1206 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1197
1198 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1199 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1200 << SDHCI_DIVIDER_HI_SHIFT;
1201 clk |= SDHCI_CLOCK_INT_EN;
1202 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1203
1204 /* Wait max 20 ms */
1205 timeout = 20;

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1466 if (host->version >= SDHCI_SPEC_300 &&
1467 (ios->power_mode == MMC_POWER_UP) &&
1468 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1469 sdhci_enable_preset_value(host, false);
1470
1471 if (!ios->clock || ios->clock != host->clock) {
1472 host->ops->set_clock(host, ios->clock);
1473 host->clock = ios->clock;
1207 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1208 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1209 << SDHCI_DIVIDER_HI_SHIFT;
1210 clk |= SDHCI_CLOCK_INT_EN;
1211 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1212
1213 /* Wait max 20 ms */
1214 timeout = 20;

--- 260 unchanged lines hidden (view full) ---

1475 if (host->version >= SDHCI_SPEC_300 &&
1476 (ios->power_mode == MMC_POWER_UP) &&
1477 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1478 sdhci_enable_preset_value(host, false);
1479
1480 if (!ios->clock || ios->clock != host->clock) {
1481 host->ops->set_clock(host, ios->clock);
1482 host->clock = ios->clock;
1483
1484 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1485 host->clock) {
1486 host->timeout_clk = host->mmc->actual_clock ?
1487 host->mmc->actual_clock / 1000 :
1488 host->clock / 1000;
1489 host->mmc->max_busy_timeout =
1490 host->ops->get_max_timeout_count ?
1491 host->ops->get_max_timeout_count(host) :
1492 1 << 27;
1493 host->mmc->max_busy_timeout /= host->timeout_clk;
1494 }
1474 }
1475
1476 sdhci_set_power(host, ios->power_mode, ios->vdd);
1477
1478 if (host->ops->platform_send_init_74_clocks)
1479 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1480
1481 host->ops->set_bus_width(host, ios->bus_width);

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1728 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1729 ctrl &= ~SDHCI_CTRL_VDD_180;
1730 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1731
1732 if (!IS_ERR(mmc->supply.vqmmc)) {
1733 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1734 3600000);
1735 if (ret) {
1495 }
1496
1497 sdhci_set_power(host, ios->power_mode, ios->vdd);
1498
1499 if (host->ops->platform_send_init_74_clocks)
1500 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1501
1502 host->ops->set_bus_width(host, ios->bus_width);

--- 246 unchanged lines hidden (view full) ---

1749 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1750 ctrl &= ~SDHCI_CTRL_VDD_180;
1751 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1752
1753 if (!IS_ERR(mmc->supply.vqmmc)) {
1754 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1755 3600000);
1756 if (ret) {
1736 pr_warning("%s: Switching to 3.3V signalling voltage "
1737 " failed\n", mmc_hostname(mmc));
1757 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1758 mmc_hostname(mmc));
1738 return -EIO;
1739 }
1740 }
1741 /* Wait for 5ms */
1742 usleep_range(5000, 5500);
1743
1744 /* 3.3V regulator output should be stable within 5 ms */
1745 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1746 if (!(ctrl & SDHCI_CTRL_VDD_180))
1747 return 0;
1748
1759 return -EIO;
1760 }
1761 }
1762 /* Wait for 5ms */
1763 usleep_range(5000, 5500);
1764
1765 /* 3.3V regulator output should be stable within 5 ms */
1766 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1767 if (!(ctrl & SDHCI_CTRL_VDD_180))
1768 return 0;
1769
1749 pr_warning("%s: 3.3V regulator output did not became stable\n",
1750 mmc_hostname(mmc));
1770 pr_warn("%s: 3.3V regulator output did not became stable\n",
1771 mmc_hostname(mmc));
1751
1752 return -EAGAIN;
1753 case MMC_SIGNAL_VOLTAGE_180:
1754 if (!IS_ERR(mmc->supply.vqmmc)) {
1755 ret = regulator_set_voltage(mmc->supply.vqmmc,
1756 1700000, 1950000);
1757 if (ret) {
1772
1773 return -EAGAIN;
1774 case MMC_SIGNAL_VOLTAGE_180:
1775 if (!IS_ERR(mmc->supply.vqmmc)) {
1776 ret = regulator_set_voltage(mmc->supply.vqmmc,
1777 1700000, 1950000);
1778 if (ret) {
1758 pr_warning("%s: Switching to 1.8V signalling voltage "
1759 " failed\n", mmc_hostname(mmc));
1779 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1780 mmc_hostname(mmc));
1760 return -EIO;
1761 }
1762 }
1763
1764 /*
1765 * Enable 1.8V Signal Enable in the Host Control2
1766 * register
1767 */
1768 ctrl |= SDHCI_CTRL_VDD_180;
1769 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1770
1771 /* 1.8V regulator output should be stable within 5 ms */
1772 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1773 if (ctrl & SDHCI_CTRL_VDD_180)
1774 return 0;
1775
1781 return -EIO;
1782 }
1783 }
1784
1785 /*
1786 * Enable 1.8V Signal Enable in the Host Control2
1787 * register
1788 */
1789 ctrl |= SDHCI_CTRL_VDD_180;
1790 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1791
1792 /* 1.8V regulator output should be stable within 5 ms */
1793 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1794 if (ctrl & SDHCI_CTRL_VDD_180)
1795 return 0;
1796
1776 pr_warning("%s: 1.8V regulator output did not became stable\n",
1777 mmc_hostname(mmc));
1797 pr_warn("%s: 1.8V regulator output did not became stable\n",
1798 mmc_hostname(mmc));
1778
1779 return -EAGAIN;
1780 case MMC_SIGNAL_VOLTAGE_120:
1781 if (!IS_ERR(mmc->supply.vqmmc)) {
1782 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1783 1300000);
1784 if (ret) {
1799
1800 return -EAGAIN;
1801 case MMC_SIGNAL_VOLTAGE_120:
1802 if (!IS_ERR(mmc->supply.vqmmc)) {
1803 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1804 1300000);
1805 if (ret) {
1785 pr_warning("%s: Switching to 1.2V signalling voltage "
1786 " failed\n", mmc_hostname(mmc));
1806 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1807 mmc_hostname(mmc));
1787 return -EIO;
1788 }
1789 }
1790 return 0;
1791 default:
1792 /* No signal voltage switch required */
1793 return 0;
1794 }

--- 441 unchanged lines hidden (view full) ---

2236 * Note: The 1.0 specification is a bit ambiguous about this
2237 * feature so there might be some problems with older
2238 * controllers.
2239 */
2240 if (host->cmd->flags & MMC_RSP_BUSY) {
2241 if (host->cmd->data)
2242 DBG("Cannot wait for busy signal when also "
2243 "doing a data transfer");
1808 return -EIO;
1809 }
1810 }
1811 return 0;
1812 default:
1813 /* No signal voltage switch required */
1814 return 0;
1815 }

--- 441 unchanged lines hidden (view full) ---

2257 * Note: The 1.0 specification is a bit ambiguous about this
2258 * feature so there might be some problems with older
2259 * controllers.
2260 */
2261 if (host->cmd->flags & MMC_RSP_BUSY) {
2262 if (host->cmd->data)
2263 DBG("Cannot wait for busy signal when also "
2264 "doing a data transfer");
2244 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2265 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2266 && !host->busy_handle) {
2267 /* Mark that command complete before busy is ended */
2268 host->busy_handle = 1;
2245 return;
2269 return;
2270 }
2246
2247 /* The controller does not support the end-of-busy IRQ,
2248 * fall through and take the SDHCI_INT_RESPONSE */
2249 }
2250
2251 if (intmask & SDHCI_INT_RESPONSE)
2252 sdhci_finish_command(host);
2253}

--- 45 unchanged lines hidden (view full) ---

2299
2300 if (!host->data) {
2301 /*
2302 * The "data complete" interrupt is also used to
2303 * indicate that a busy state has ended. See comment
2304 * above in sdhci_cmd_irq().
2305 */
2306 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2271
2272 /* The controller does not support the end-of-busy IRQ,
2273 * fall through and take the SDHCI_INT_RESPONSE */
2274 }
2275
2276 if (intmask & SDHCI_INT_RESPONSE)
2277 sdhci_finish_command(host);
2278}

--- 45 unchanged lines hidden (view full) ---

2324
2325 if (!host->data) {
2326 /*
2327 * The "data complete" interrupt is also used to
2328 * indicate that a busy state has ended. See comment
2329 * above in sdhci_cmd_irq().
2330 */
2331 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2332 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2333 host->cmd->error = -ETIMEDOUT;
2334 tasklet_schedule(&host->finish_tasklet);
2335 return;
2336 }
2307 if (intmask & SDHCI_INT_DATA_END) {
2337 if (intmask & SDHCI_INT_DATA_END) {
2308 sdhci_finish_command(host);
2338 /*
2339 * Some cards handle busy-end interrupt
2340 * before the command completed, so make
2341 * sure we do things in the proper order.
2342 */
2343 if (host->busy_handle)
2344 sdhci_finish_command(host);
2345 else
2346 host->busy_handle = 1;
2309 return;
2310 }
2311 }
2312
2313 pr_err("%s: Got data interrupt 0x%08x even "
2314 "though no data operation was in progress.\n",
2315 mmc_hostname(host->mmc), (unsigned)intmask);
2316 sdhci_dumpregs(host);

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2529 val |= mask ;
2530 /* Avoid fake wake up */
2531 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2532 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2533 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2534}
2535EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2536
2347 return;
2348 }
2349 }
2350
2351 pr_err("%s: Got data interrupt 0x%08x even "
2352 "though no data operation was in progress.\n",
2353 mmc_hostname(host->mmc), (unsigned)intmask);
2354 sdhci_dumpregs(host);

--- 212 unchanged lines hidden (view full) ---

2567 val |= mask ;
2568 /* Avoid fake wake up */
2569 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2570 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2571 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2572}
2573EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2574
2537void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2575static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2538{
2539 u8 val;
2540 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2541 | SDHCI_WAKE_ON_INT;
2542
2543 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2544 val &= ~mask;
2545 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2546}
2576{
2577 u8 val;
2578 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2579 | SDHCI_WAKE_ON_INT;
2580
2581 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2582 val &= ~mask;
2583 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2584}
2547EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups);
2548
2549int sdhci_suspend_host(struct sdhci_host *host)
2550{
2551 sdhci_disable_card_detection(host);
2552
2553 /* Disable tuning since we are suspending */
2554 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2555 del_timer_sync(&host->tuning_timer);

--- 246 unchanged lines hidden (view full) ---

2802 (host->flags & SDHCI_USE_ADMA)) {
2803 DBG("Disabling ADMA as it is marked broken\n");
2804 host->flags &= ~SDHCI_USE_ADMA;
2805 }
2806
2807 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2808 if (host->ops->enable_dma) {
2809 if (host->ops->enable_dma(host)) {
2585
2586int sdhci_suspend_host(struct sdhci_host *host)
2587{
2588 sdhci_disable_card_detection(host);
2589
2590 /* Disable tuning since we are suspending */
2591 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2592 del_timer_sync(&host->tuning_timer);

--- 246 unchanged lines hidden (view full) ---

2839 (host->flags & SDHCI_USE_ADMA)) {
2840 DBG("Disabling ADMA as it is marked broken\n");
2841 host->flags &= ~SDHCI_USE_ADMA;
2842 }
2843
2844 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2845 if (host->ops->enable_dma) {
2846 if (host->ops->enable_dma(host)) {
2810 pr_warning("%s: No suitable DMA "
2811 "available. Falling back to PIO.\n",
2847 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
2812 mmc_hostname(mmc));
2813 host->flags &=
2814 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2815 }
2816 }
2817 }
2818
2819 if (host->flags & SDHCI_USE_ADMA) {

--- 5 unchanged lines hidden (view full) ---

2825 host->adma_desc = dma_alloc_coherent(mmc_dev(mmc),
2826 ADMA_SIZE, &host->adma_addr,
2827 GFP_KERNEL);
2828 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2829 if (!host->adma_desc || !host->align_buffer) {
2830 dma_free_coherent(mmc_dev(mmc), ADMA_SIZE,
2831 host->adma_desc, host->adma_addr);
2832 kfree(host->align_buffer);
2848 mmc_hostname(mmc));
2849 host->flags &=
2850 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2851 }
2852 }
2853 }
2854
2855 if (host->flags & SDHCI_USE_ADMA) {

--- 5 unchanged lines hidden (view full) ---

2861 host->adma_desc = dma_alloc_coherent(mmc_dev(mmc),
2862 ADMA_SIZE, &host->adma_addr,
2863 GFP_KERNEL);
2864 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2865 if (!host->adma_desc || !host->align_buffer) {
2866 dma_free_coherent(mmc_dev(mmc), ADMA_SIZE,
2867 host->adma_desc, host->adma_addr);
2868 kfree(host->align_buffer);
2833 pr_warning("%s: Unable to allocate ADMA "
2834 "buffers. Falling back to standard DMA.\n",
2869 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2835 mmc_hostname(mmc));
2836 host->flags &= ~SDHCI_USE_ADMA;
2837 host->adma_desc = NULL;
2838 host->align_buffer = NULL;
2839 } else if (host->adma_addr & 3) {
2870 mmc_hostname(mmc));
2871 host->flags &= ~SDHCI_USE_ADMA;
2872 host->adma_desc = NULL;
2873 host->align_buffer = NULL;
2874 } else if (host->adma_addr & 3) {
2840 pr_warning("%s: unable to allocate aligned ADMA descriptor\n",
2841 mmc_hostname(mmc));
2875 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
2876 mmc_hostname(mmc));
2842 host->flags &= ~SDHCI_USE_ADMA;
2843 dma_free_coherent(mmc_dev(mmc), ADMA_SIZE,
2844 host->adma_desc, host->adma_addr);
2845 kfree(host->align_buffer);
2846 host->adma_desc = NULL;
2847 host->align_buffer = NULL;
2848 }
2849 }

--- 53 unchanged lines hidden (view full) ---

2903 if (host->clk_mul) {
2904 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2905 mmc->f_max = host->max_clk * host->clk_mul;
2906 } else
2907 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2908 } else
2909 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2910
2877 host->flags &= ~SDHCI_USE_ADMA;
2878 dma_free_coherent(mmc_dev(mmc), ADMA_SIZE,
2879 host->adma_desc, host->adma_addr);
2880 kfree(host->align_buffer);
2881 host->adma_desc = NULL;
2882 host->align_buffer = NULL;
2883 }
2884 }

--- 53 unchanged lines hidden (view full) ---

2938 if (host->clk_mul) {
2939 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2940 mmc->f_max = host->max_clk * host->clk_mul;
2941 } else
2942 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2943 } else
2944 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2945
2911 host->timeout_clk =
2912 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2913 if (host->timeout_clk == 0) {
2914 if (host->ops->get_timeout_clock) {
2915 host->timeout_clk = host->ops->get_timeout_clock(host);
2916 } else if (!(host->quirks &
2917 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2918 pr_err("%s: Hardware doesn't specify timeout clock "
2919 "frequency.\n", mmc_hostname(mmc));
2920 return -ENODEV;
2946 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2947 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
2948 SDHCI_TIMEOUT_CLK_SHIFT;
2949 if (host->timeout_clk == 0) {
2950 if (host->ops->get_timeout_clock) {
2951 host->timeout_clk =
2952 host->ops->get_timeout_clock(host);
2953 } else {
2954 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
2955 mmc_hostname(mmc));
2956 return -ENODEV;
2957 }
2921 }
2958 }
2922 }
2923 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2924 host->timeout_clk *= 1000;
2925
2959
2926 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2927 host->timeout_clk = mmc->f_max / 1000;
2960 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2961 host->timeout_clk *= 1000;
2928
2962
2929 mmc->max_busy_timeout = (1 << 27) / host->timeout_clk;
2963 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
2964 host->ops->get_max_timeout_count(host) : 1 << 27;
2965 mmc->max_busy_timeout /= host->timeout_clk;
2966 }
2930
2931 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2932 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2933
2934 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2935 host->flags |= SDHCI_AUTO_CMD12;
2936
2937 /* Auto-CMD23 stuff only works in ADMA or PIO. */

--- 55 unchanged lines hidden (view full) ---

2993 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2994
2995 /* SDR104 supports also implies SDR50 support */
2996 if (caps[1] & SDHCI_SUPPORT_SDR104) {
2997 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2998 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
2999 * field can be promoted to support HS200.
3000 */
2967
2968 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2969 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2970
2971 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2972 host->flags |= SDHCI_AUTO_CMD12;
2973
2974 /* Auto-CMD23 stuff only works in ADMA or PIO. */

--- 55 unchanged lines hidden (view full) ---

3030 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3031
3032 /* SDR104 supports also implies SDR50 support */
3033 if (caps[1] & SDHCI_SUPPORT_SDR104) {
3034 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3035 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3036 * field can be promoted to support HS200.
3037 */
3001 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3038 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200)) {
3002 mmc->caps2 |= MMC_CAP2_HS200;
3039 mmc->caps2 |= MMC_CAP2_HS200;
3040 if (IS_ERR(mmc->supply.vqmmc) ||
3041 !regulator_is_supported_voltage
3042 (mmc->supply.vqmmc, 1100000, 1300000))
3043 mmc->caps2 &= ~MMC_CAP2_HS200_1_2V_SDR;
3044 }
3003 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3004 mmc->caps |= MMC_CAP_UHS_SDR50;
3005
3006 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3007 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3008 mmc->caps |= MMC_CAP_UHS_DDR50;
3009
3010 /* Does the host need tuning for SDR50? */

--- 33 unchanged lines hidden (view full) ---

3044 * According to SD Host Controller spec v3.00, if the Host System
3045 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3046 * the value is meaningful only if Voltage Support in the Capabilities
3047 * register is set. The actual current value is 4 times the register
3048 * value.
3049 */
3050 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3051 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3045 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3046 mmc->caps |= MMC_CAP_UHS_SDR50;
3047
3048 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3049 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3050 mmc->caps |= MMC_CAP_UHS_DDR50;
3051
3052 /* Does the host need tuning for SDR50? */

--- 33 unchanged lines hidden (view full) ---

3086 * According to SD Host Controller spec v3.00, if the Host System
3087 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3088 * the value is meaningful only if Voltage Support in the Capabilities
3089 * register is set. The actual current value is 4 times the register
3090 * value.
3091 */
3092 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3093 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3052 u32 curr = regulator_get_current_limit(mmc->supply.vmmc);
3094 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3053 if (curr > 0) {
3054
3055 /* convert to SDHCI_MAX_CURRENT format */
3056 curr = curr/1000; /* convert to mA */
3057 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3058
3059 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3060 max_current_caps =

--- 92 unchanged lines hidden (view full) ---

3153 * is specified in the capabilities register.
3154 */
3155 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3156 mmc->max_blk_size = 2;
3157 } else {
3158 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3159 SDHCI_MAX_BLOCK_SHIFT;
3160 if (mmc->max_blk_size >= 3) {
3095 if (curr > 0) {
3096
3097 /* convert to SDHCI_MAX_CURRENT format */
3098 curr = curr/1000; /* convert to mA */
3099 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3100
3101 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3102 max_current_caps =

--- 92 unchanged lines hidden (view full) ---

3195 * is specified in the capabilities register.
3196 */
3197 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3198 mmc->max_blk_size = 2;
3199 } else {
3200 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3201 SDHCI_MAX_BLOCK_SHIFT;
3202 if (mmc->max_blk_size >= 3) {
3161 pr_warning("%s: Invalid maximum block size, "
3162 "assuming 512 bytes\n", mmc_hostname(mmc));
3203 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3204 mmc_hostname(mmc));
3163 mmc->max_blk_size = 0;
3164 }
3165 }
3166
3167 mmc->max_blk_size = 512 << mmc->max_blk_size;
3168
3169 /*
3170 * Maximum block count.

--- 173 unchanged lines hidden --- 		3205 mmc->max_blk_size = 0;
3206 }
3207 }
3208
3209 mmc->max_blk_size = 512 << mmc->max_blk_size;
3210
3211 /*
3212 * Maximum block count.

--- 173 unchanged lines hidden ---