sdhci-pxav3.c (e5451c8f8330e03ad3cfa16048b4daf961af434f) sdhci-pxav3.c (0ca33b4ad9cfc133bb3d93eec1ad0eea83d6f252)
1/*
2 * Copyright (C) 2010 Marvell International Ltd.
3 * Zhangfei Gao <zhangfei.gao@marvell.com>
4 * Kevin Wang <dwang4@marvell.com>
5 * Mingwei Wang <mwwang@marvell.com>
6 * Philip Rakity <prakity@marvell.com>
7 * Mark Brown <markb@marvell.com>
8 *

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132{
133 struct device_node *np = pdev->dev.of_node;
134 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
135 struct sdhci_pxa *pxa = pltfm_host->priv;
136 struct resource *res;
137
138 host->quirks &= ~SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
139 host->quirks |= SDHCI_QUIRK_MISSING_CAPS;
1/*
2 * Copyright (C) 2010 Marvell International Ltd.
3 * Zhangfei Gao <zhangfei.gao@marvell.com>
4 * Kevin Wang <dwang4@marvell.com>
5 * Mingwei Wang <mwwang@marvell.com>
6 * Philip Rakity <prakity@marvell.com>
7 * Mark Brown <markb@marvell.com>
8 *

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132{
133 struct device_node *np = pdev->dev.of_node;
134 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
135 struct sdhci_pxa *pxa = pltfm_host->priv;
136 struct resource *res;
137
138 host->quirks &= ~SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
139 host->quirks |= SDHCI_QUIRK_MISSING_CAPS;
140
141 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
142 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
143
140 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
141 "conf-sdio3");
142 if (res) {
143 pxa->sdio3_conf_reg = devm_ioremap_resource(&pdev->dev, res);
144 if (IS_ERR(pxa->sdio3_conf_reg))
145 return PTR_ERR(pxa->sdio3_conf_reg);
146 } else {
147 /*
148 * According to erratum 'FE-2946959' both SDR50 and DDR50
149 * modes require specific clock adjustments in SDIO3
150 * Configuration register, if the adjustment is not done,
151 * remove them from the capabilities.
152 */
144 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
145 "conf-sdio3");
146 if (res) {
147 pxa->sdio3_conf_reg = devm_ioremap_resource(&pdev->dev, res);
148 if (IS_ERR(pxa->sdio3_conf_reg))
149 return PTR_ERR(pxa->sdio3_conf_reg);
150 } else {
151 /*
152 * According to erratum 'FE-2946959' both SDR50 and DDR50
153 * modes require specific clock adjustments in SDIO3
154 * Configuration register, if the adjustment is not done,
155 * remove them from the capabilities.
156 */
153 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
154 host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
155
156 dev_warn(&pdev->dev, "conf-sdio3 register not found: disabling SDR50 and DDR50 modes.\nConsider updating your dtb\n");
157 }
158
159 /*
160 * According to erratum 'ERR-7878951' Armada 38x SDHCI
161 * controller has different capabilities than the ones shown
162 * in its registers
163 */
157 host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
158
159 dev_warn(&pdev->dev, "conf-sdio3 register not found: disabling SDR50 and DDR50 modes.\nConsider updating your dtb\n");
160 }
161
162 /*
163 * According to erratum 'ERR-7878951' Armada 38x SDHCI
164 * controller has different capabilities than the ones shown
165 * in its registers
166 */
164 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
165 if (of_property_read_bool(np, "no-1-8-v")) {
166 host->caps &= ~SDHCI_CAN_VDD_180;
167 host->mmc->caps &= ~MMC_CAP_1_8V_DDR;
168 } else {
169 host->caps &= ~SDHCI_CAN_VDD_330;
170 }
171 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_USE_SDR50_TUNING);
172

--- 422 unchanged lines hidden --- 		167 if (of_property_read_bool(np, "no-1-8-v")) {
168 host->caps &= ~SDHCI_CAN_VDD_180;
169 host->mmc->caps &= ~MMC_CAP_1_8V_DDR;
170 } else {
171 host->caps &= ~SDHCI_CAN_VDD_330;
172 }
173 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_USE_SDR50_TUNING);
174

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