| sdhci-pxav3.c (a976c2951d8f376112361830aa7762beff83a205) | sdhci-pxav3.c (d35ade8ff7e21d2a8ac57a994cf2cef3b599e9e3) |
|---|---|
| 1/* 2 * Copyright (C) 2010 Marvell International Ltd. 3 * Zhangfei Gao <zhangfei.gao@marvell.com> 4 * Kevin Wang <dwang4@marvell.com> 5 * Mingwei Wang <mwwang@marvell.com> 6 * Philip Rakity <prakity@marvell.com> 7 * Mark Brown <markb@marvell.com> 8 * --- 323 unchanged lines hidden (view full) --- 332 .set_power = pxav3_set_power, 333 .platform_send_init_74_clocks = pxav3_gen_init_74_clocks, 334 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 335 .set_bus_width = sdhci_set_bus_width, 336 .reset = pxav3_reset, 337 .set_uhs_signaling = pxav3_set_uhs_signaling, 338}; 339 | 1/* 2 * Copyright (C) 2010 Marvell International Ltd. 3 * Zhangfei Gao <zhangfei.gao@marvell.com> 4 * Kevin Wang <dwang4@marvell.com> 5 * Mingwei Wang <mwwang@marvell.com> 6 * Philip Rakity <prakity@marvell.com> 7 * Mark Brown <markb@marvell.com> 8 * --- 323 unchanged lines hidden (view full) --- 332 .set_power = pxav3_set_power, 333 .platform_send_init_74_clocks = pxav3_gen_init_74_clocks, 334 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 335 .set_bus_width = sdhci_set_bus_width, 336 .reset = pxav3_reset, 337 .set_uhs_signaling = pxav3_set_uhs_signaling, 338}; 339 |
| 340static struct sdhci_pltfm_data sdhci_pxav3_pdata = { | 340static const struct sdhci_pltfm_data sdhci_pxav3_pdata = { |
| 341 .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK 342 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC 343 | SDHCI_QUIRK_32BIT_ADMA_SIZE 344 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 345 .ops = &pxav3_sdhci_ops, 346}; 347 348#ifdef CONFIG_OF --- 259 unchanged lines hidden --- | 341 .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK 342 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC 343 | SDHCI_QUIRK_32BIT_ADMA_SIZE 344 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 345 .ops = &pxav3_sdhci_ops, 346}; 347 348#ifdef CONFIG_OF --- 259 unchanged lines hidden --- |