sdhci-pxav2.c (03231f9b781f24205c0af0398ce3cbef70090939) sdhci-pxav2.c (1771059cf5f9c09e37ef6315df8acf120f2642fc)
1/*
2 * Copyright (C) 2010 Marvell International Ltd.
3 * Zhangfei Gao <zhangfei.gao@marvell.com>
4 * Kevin Wang <dwang4@marvell.com>
5 * Jun Nie <njun@marvell.com>
6 * Qiming Wu <wuqm@marvell.com>
7 * Philip Rakity <prakity@marvell.com>
8 *

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107 else
108 ctrl &= ~SDHCI_CTRL_4BITBUS;
109 }
110 writew(tmp, host->ioaddr + SD_CE_ATA_2);
111 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
112}
113
114static const struct sdhci_ops pxav2_sdhci_ops = {
1/*
2 * Copyright (C) 2010 Marvell International Ltd.
3 * Zhangfei Gao <zhangfei.gao@marvell.com>
4 * Kevin Wang <dwang4@marvell.com>
5 * Jun Nie <njun@marvell.com>
6 * Qiming Wu <wuqm@marvell.com>
7 * Philip Rakity <prakity@marvell.com>
8 *

--- 98 unchanged lines hidden (view full) ---

107 else
108 ctrl &= ~SDHCI_CTRL_4BITBUS;
109 }
110 writew(tmp, host->ioaddr + SD_CE_ATA_2);
111 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
112}
113
114static const struct sdhci_ops pxav2_sdhci_ops = {
115 .set_clock = sdhci_set_clock,
115 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
116 .set_bus_width = pxav2_mmc_set_bus_width,
117 .reset = pxav2_reset,
118};
119
120#ifdef CONFIG_OF
121static const struct of_device_id sdhci_pxav2_of_match[] = {
122 {

--- 155 unchanged lines hidden --- 		116 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
117 .set_bus_width = pxav2_mmc_set_bus_width,
118 .reset = pxav2_reset,
119};
120
121#ifdef CONFIG_OF
122static const struct of_device_id sdhci_pxav2_of_match[] = {
123 {

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