sdhci-esdhc.h (53279f36dccffc26ff536003fd6bb97cc21c3b82) sdhci-esdhc.h (8ba9580a8045b6d5fed66e13b77599f3d8a77fed)
1/*
2 * Freescale eSDHC controller driver generics for OF and pltfm.
3 *
4 * Copyright (c) 2007 Freescale Semiconductor, Inc.
5 * Copyright (c) 2009 MontaVista Software, Inc.
6 * Copyright (c) 2010 Pengutronix e.K.
7 * Author: Wolfram Sang <w.sang@pengutronix.de>
8 *

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37#define ESDHC_HOST_CONTROL_LE 0x20
38
39/* OF-specific */
40#define ESDHC_DMA_SYSCTL 0x40c
41#define ESDHC_DMA_SNOOP 0x00000040
42
43#define ESDHC_HOST_CONTROL_RES 0x05
44
1/*
2 * Freescale eSDHC controller driver generics for OF and pltfm.
3 *
4 * Copyright (c) 2007 Freescale Semiconductor, Inc.
5 * Copyright (c) 2009 MontaVista Software, Inc.
6 * Copyright (c) 2010 Pengutronix e.K.
7 * Author: Wolfram Sang <w.sang@pengutronix.de>
8 *

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37#define ESDHC_HOST_CONTROL_LE 0x20
38
39/* OF-specific */
40#define ESDHC_DMA_SYSCTL 0x40c
41#define ESDHC_DMA_SNOOP 0x00000040
42
43#define ESDHC_HOST_CONTROL_RES 0x05
44
45static inline void esdhc_set_clock(struct sdhci_host *host, unsigned int clock)
45static inline void esdhc_set_clock(struct sdhci_host *host, unsigned int clock,
46 unsigned int host_clock)
46{
47 int pre_div = 2;
48 int div = 1;
49 u32 temp;
50
51 if (clock == 0)
52 goto out;
53
54 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
55 temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
56 | ESDHC_CLOCK_MASK);
57 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
58
47{
48 int pre_div = 2;
49 int div = 1;
50 u32 temp;
51
52 if (clock == 0)
53 goto out;
54
55 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
56 temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
57 | ESDHC_CLOCK_MASK);
58 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
59
59 while (host->max_clk / pre_div / 16 > clock && pre_div < 256)
60 while (host_clock / pre_div / 16 > clock && pre_div < 256)
60 pre_div *= 2;
61
61 pre_div *= 2;
62
62 while (host->max_clk / pre_div / div > clock && div < 16)
63 while (host_clock / pre_div / div > clock && div < 16)
63 div++;
64
65 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
64 div++;
65
66 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
66 clock, host->max_clk / pre_div / div);
67 clock, host_clock / pre_div / div);
67
68 pre_div >>= 1;
69 div--;
70
71 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
72 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
73 | (div << ESDHC_DIVIDER_SHIFT)
74 | (pre_div << ESDHC_PREDIV_SHIFT));
75 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
76 mdelay(1);
77out:
78 host->clock = clock;
79}
80
81#endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */
68
69 pre_div >>= 1;
70 div--;
71
72 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
73 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
74 | (div << ESDHC_DIVIDER_SHIFT)
75 | (pre_div << ESDHC_PREDIV_SHIFT));
76 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
77 mdelay(1);
78out:
79 host->clock = clock;
80}
81
82#endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */