pch_phub.c (94bd217e2d683719ab21a4ac117d8a1b91cbedc9) pch_phub.c (dd7d7fea29c18b818e94f252a76f495490d399c3)
1/*
2 * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
7 *
8 * This program is distributed in the hope that it will be useful,

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85#define PCH_PHUB_BUS_SLAVE_CONTROL_REG 0x0014
86#define PCH_PHUB_DEADLOCK_AVOID_TYPE_REG 0x0018
87#define PCH_PHUB_INTPIN_REG_WPERMIT_REG0 0x0020
88#define PCH_PHUB_INTPIN_REG_WPERMIT_REG1 0x0024
89#define PCH_PHUB_INTPIN_REG_WPERMIT_REG2 0x0028
90#define PCH_PHUB_INTPIN_REG_WPERMIT_REG3 0x002C
91#define PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE 0x0040
92#define CLKCFG_REG_OFFSET 0x500
1/*
2 * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
7 *
8 * This program is distributed in the hope that it will be useful,

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85#define PCH_PHUB_BUS_SLAVE_CONTROL_REG 0x0014
86#define PCH_PHUB_DEADLOCK_AVOID_TYPE_REG 0x0018
87#define PCH_PHUB_INTPIN_REG_WPERMIT_REG0 0x0020
88#define PCH_PHUB_INTPIN_REG_WPERMIT_REG1 0x0024
89#define PCH_PHUB_INTPIN_REG_WPERMIT_REG2 0x0028
90#define PCH_PHUB_INTPIN_REG_WPERMIT_REG3 0x002C
91#define PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE 0x0040
92#define CLKCFG_REG_OFFSET 0x500
93#define FUNCSEL_REG_OFFSET 0x508
93
94#define PCH_PHUB_OROM_SIZE 15360
95
96/**
97 * struct pch_phub_reg - PHUB register structure
98 * @phub_id_reg: PHUB_ID register val
99 * @q_pri_val_reg: QUEUE_PRI_VAL register val
100 * @rc_q_maxsize_reg: RC_QUEUE_MAXSIZE register val
101 * @bri_q_maxsize_reg: BRI_QUEUE_MAXSIZE register val
102 * @comp_resp_timeout_reg: COMP_RESP_TIMEOUT register val
103 * @bus_slave_control_reg: BUS_SLAVE_CONTROL_REG register val
104 * @deadlock_avoid_type_reg: DEADLOCK_AVOID_TYPE register val
105 * @intpin_reg_wpermit_reg0: INTPIN_REG_WPERMIT register 0 val
106 * @intpin_reg_wpermit_reg1: INTPIN_REG_WPERMIT register 1 val
107 * @intpin_reg_wpermit_reg2: INTPIN_REG_WPERMIT register 2 val
108 * @intpin_reg_wpermit_reg3: INTPIN_REG_WPERMIT register 3 val
109 * @int_reduce_control_reg: INT_REDUCE_CONTROL registers val
110 * @clkcfg_reg: CLK CFG register val
94
95#define PCH_PHUB_OROM_SIZE 15360
96
97/**
98 * struct pch_phub_reg - PHUB register structure
99 * @phub_id_reg: PHUB_ID register val
100 * @q_pri_val_reg: QUEUE_PRI_VAL register val
101 * @rc_q_maxsize_reg: RC_QUEUE_MAXSIZE register val
102 * @bri_q_maxsize_reg: BRI_QUEUE_MAXSIZE register val
103 * @comp_resp_timeout_reg: COMP_RESP_TIMEOUT register val
104 * @bus_slave_control_reg: BUS_SLAVE_CONTROL_REG register val
105 * @deadlock_avoid_type_reg: DEADLOCK_AVOID_TYPE register val
106 * @intpin_reg_wpermit_reg0: INTPIN_REG_WPERMIT register 0 val
107 * @intpin_reg_wpermit_reg1: INTPIN_REG_WPERMIT register 1 val
108 * @intpin_reg_wpermit_reg2: INTPIN_REG_WPERMIT register 2 val
109 * @intpin_reg_wpermit_reg3: INTPIN_REG_WPERMIT register 3 val
110 * @int_reduce_control_reg: INT_REDUCE_CONTROL registers val
111 * @clkcfg_reg: CLK CFG register val
112 * @funcsel_reg: Function select register value
111 * @pch_phub_base_address: Register base address
112 * @pch_phub_extrom_base_address: external rom base address
113 * @pch_mac_start_address: MAC address area start address
114 * @pch_opt_rom_start_address: Option ROM start address
115 * @ioh_type: Save IOH type
116 */
117struct pch_phub_reg {
118 u32 phub_id_reg;

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123 u32 bus_slave_control_reg;
124 u32 deadlock_avoid_type_reg;
125 u32 intpin_reg_wpermit_reg0;
126 u32 intpin_reg_wpermit_reg1;
127 u32 intpin_reg_wpermit_reg2;
128 u32 intpin_reg_wpermit_reg3;
129 u32 int_reduce_control_reg[MAX_NUM_INT_REDUCE_CONTROL_REG];
130 u32 clkcfg_reg;
113 * @pch_phub_base_address: Register base address
114 * @pch_phub_extrom_base_address: external rom base address
115 * @pch_mac_start_address: MAC address area start address
116 * @pch_opt_rom_start_address: Option ROM start address
117 * @ioh_type: Save IOH type
118 */
119struct pch_phub_reg {
120 u32 phub_id_reg;

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125 u32 bus_slave_control_reg;
126 u32 deadlock_avoid_type_reg;
127 u32 intpin_reg_wpermit_reg0;
128 u32 intpin_reg_wpermit_reg1;
129 u32 intpin_reg_wpermit_reg2;
130 u32 intpin_reg_wpermit_reg3;
131 u32 int_reduce_control_reg[MAX_NUM_INT_REDUCE_CONTROL_REG];
132 u32 clkcfg_reg;
133 u32 funcsel_reg;
131 void __iomem *pch_phub_base_address;
132 void __iomem *pch_phub_extrom_base_address;
133 u32 pch_mac_start_address;
134 u32 pch_opt_rom_start_address;
135 int ioh_type;
136};
137
138/* SROM SPEC for MAC address assignment offset */

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206 for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) {
207 chip->int_reduce_control_reg[i] =
208 ioread32(p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i);
209 dev_dbg(&pdev->dev, "%s : "
210 "chip->int_reduce_control_reg[%d]=%x\n",
211 __func__, i, chip->int_reduce_control_reg[i]);
212 }
213 chip->clkcfg_reg = ioread32(p + CLKCFG_REG_OFFSET);
134 void __iomem *pch_phub_base_address;
135 void __iomem *pch_phub_extrom_base_address;
136 u32 pch_mac_start_address;
137 u32 pch_opt_rom_start_address;
138 int ioh_type;
139};
140
141/* SROM SPEC for MAC address assignment offset */

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209 for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) {
210 chip->int_reduce_control_reg[i] =
211 ioread32(p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i);
212 dev_dbg(&pdev->dev, "%s : "
213 "chip->int_reduce_control_reg[%d]=%x\n",
214 __func__, i, chip->int_reduce_control_reg[i]);
215 }
216 chip->clkcfg_reg = ioread32(p + CLKCFG_REG_OFFSET);
217 if ((chip->ioh_type == 2) || (chip->ioh_type == 4))
218 chip->funcsel_reg = ioread32(p + FUNCSEL_REG_OFFSET);
214}
215
216/* pch_phub_restore_reg_conf - restore register configuration */
217static void pch_phub_restore_reg_conf(struct pci_dev *pdev)
218{
219 unsigned int i;
220 struct pch_phub_reg *chip = pci_get_drvdata(pdev);
221 void __iomem *p;

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266 iowrite32(chip->int_reduce_control_reg[i],
267 p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i);
268 dev_dbg(&pdev->dev, "%s : "
269 "chip->int_reduce_control_reg[%d]=%x\n",
270 __func__, i, chip->int_reduce_control_reg[i]);
271 }
272
273 iowrite32(chip->clkcfg_reg, p + CLKCFG_REG_OFFSET);
219}
220
221/* pch_phub_restore_reg_conf - restore register configuration */
222static void pch_phub_restore_reg_conf(struct pci_dev *pdev)
223{
224 unsigned int i;
225 struct pch_phub_reg *chip = pci_get_drvdata(pdev);
226 void __iomem *p;

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271 iowrite32(chip->int_reduce_control_reg[i],
272 p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i);
273 dev_dbg(&pdev->dev, "%s : "
274 "chip->int_reduce_control_reg[%d]=%x\n",
275 __func__, i, chip->int_reduce_control_reg[i]);
276 }
277
278 iowrite32(chip->clkcfg_reg, p + CLKCFG_REG_OFFSET);
279 if ((chip->ioh_type == 2) || (chip->ioh_type == 4))
280 iowrite32(chip->funcsel_reg, p + FUNCSEL_REG_OFFSET);
274}
275
276/**
277 * pch_phub_read_serial_rom() - Reading Serial ROM
278 * @offset_address: Serial ROM offset address to read.
279 * @data: Read buffer for specified Serial ROM value.
280 */
281static void pch_phub_read_serial_rom(struct pch_phub_reg *chip,

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282
283/**
284 * pch_phub_read_serial_rom() - Reading Serial ROM
285 * @offset_address: Serial ROM offset address to read.
286 * @data: Read buffer for specified Serial ROM value.
287 */
288static void pch_phub_read_serial_rom(struct pch_phub_reg *chip,

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