mptbase.c (d335cc38c75e28407455463444b912b09c92daec) mptbase.c (3fadc59d603caf70e7a5295158e4f6eb06dffb8f)
1/*
2 * linux/drivers/message/fusion/mptbase.c
3 * This is the Fusion MPT base driver which supports multiple
4 * (SCSI + LAN) specialized protocol drivers.
5 * For use with LSI Logic PCI chip/adapter(s)
6 * running LSI Logic Fusion MPT (Message Passing Technology) firmware.
7 *
8 * Copyright (c) 1999-2005 LSI Logic Corporation

--- 172 unchanged lines hidden (view full) ---

181static void __exit fusion_exit (void);
182
183#define CHIPREG_READ32(addr) readl_relaxed(addr)
184#define CHIPREG_READ32_dmasync(addr) readl(addr)
185#define CHIPREG_WRITE32(addr,val) writel(val, addr)
186#define CHIPREG_PIO_WRITE32(addr,val) outl(val, (unsigned long)addr)
187#define CHIPREG_PIO_READ32(addr) inl((unsigned long)addr)
188
1/*
2 * linux/drivers/message/fusion/mptbase.c
3 * This is the Fusion MPT base driver which supports multiple
4 * (SCSI + LAN) specialized protocol drivers.
5 * For use with LSI Logic PCI chip/adapter(s)
6 * running LSI Logic Fusion MPT (Message Passing Technology) firmware.
7 *
8 * Copyright (c) 1999-2005 LSI Logic Corporation

--- 172 unchanged lines hidden (view full) ---

181static void __exit fusion_exit (void);
182
183#define CHIPREG_READ32(addr) readl_relaxed(addr)
184#define CHIPREG_READ32_dmasync(addr) readl(addr)
185#define CHIPREG_WRITE32(addr,val) writel(val, addr)
186#define CHIPREG_PIO_WRITE32(addr,val) outl(val, (unsigned long)addr)
187#define CHIPREG_PIO_READ32(addr) inl((unsigned long)addr)
188
189static void
190pci_disable_io_access(struct pci_dev *pdev)
191{
192 u16 command_reg;
193
194 pci_read_config_word(pdev, PCI_COMMAND, &command_reg);
195 command_reg &= ~1;
196 pci_write_config_word(pdev, PCI_COMMAND, command_reg);
197}
198
199static void
200pci_enable_io_access(struct pci_dev *pdev)
201{
202 u16 command_reg;
203
204 pci_read_config_word(pdev, PCI_COMMAND, &command_reg);
205 command_reg |= 1;
206 pci_write_config_word(pdev, PCI_COMMAND, command_reg);
207}
208
189/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
190/*
191 * mpt_interrupt - MPT adapter (IOC) specific interrupt handler.
192 * @irq: irq number (not used)
193 * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
194 * @r: pt_regs pointer (not used)
195 *
196 * This routine is registered via the request_irq() kernel API call,

--- 959 unchanged lines hidden (view full) ---

1156 ioc->bus_type = FC;
1157 /* 919X Chip Fix. Set Split transactions level
1158 * for PCIX. Set MOST bits to zero.
1159 */
1160 pci_read_config_byte(pdev, 0x6a, &pcixcmd);
1161 pcixcmd &= 0x8F;
1162 pci_write_config_byte(pdev, 0x6a, pcixcmd);
1163 }
209/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
210/*
211 * mpt_interrupt - MPT adapter (IOC) specific interrupt handler.
212 * @irq: irq number (not used)
213 * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
214 * @r: pt_regs pointer (not used)
215 *
216 * This routine is registered via the request_irq() kernel API call,

--- 959 unchanged lines hidden (view full) ---

1176 ioc->bus_type = FC;
1177 /* 919X Chip Fix. Set Split transactions level
1178 * for PCIX. Set MOST bits to zero.
1179 */
1180 pci_read_config_byte(pdev, 0x6a, &pcixcmd);
1181 pcixcmd &= 0x8F;
1182 pci_write_config_byte(pdev, 0x6a, pcixcmd);
1183 }
1184 else if (pdev->device == MPI_MANUFACTPAGE_DEVICEID_FC939X) {
1185 ioc->prod_name = "LSIFC939X";
1186 ioc->bus_type = FC;
1187 ioc->errata_flag_1064 = 1;
1188 }
1189 else if (pdev->device == MPI_MANUFACTPAGE_DEVICEID_FC949X) {
1190 ioc->prod_name = "LSIFC949X";
1191 ioc->bus_type = FC;
1192 ioc->errata_flag_1064 = 1;
1193 }
1164 else if (pdev->device == MPI_MANUFACTPAGE_DEVID_53C1030) {
1165 ioc->prod_name = "LSI53C1030";
1166 ioc->bus_type = SCSI;
1167 /* 1030 Chip Fix. Disable Split transactions
1168 * for PCIX. Set MOST bits to zero if Rev < C0( = 8).
1169 */
1170 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &revision);
1171 if (revision < C0_1030) {
1172 pci_read_config_byte(pdev, 0x6a, &pcixcmd);
1173 pcixcmd &= 0x8F;
1174 pci_write_config_byte(pdev, 0x6a, pcixcmd);
1175 }
1176 }
1177 else if (pdev->device == MPI_MANUFACTPAGE_DEVID_1030_53C1035) {
1178 ioc->prod_name = "LSI53C1035";
1179 ioc->bus_type = SCSI;
1180 }
1181
1194 else if (pdev->device == MPI_MANUFACTPAGE_DEVID_53C1030) {
1195 ioc->prod_name = "LSI53C1030";
1196 ioc->bus_type = SCSI;
1197 /* 1030 Chip Fix. Disable Split transactions
1198 * for PCIX. Set MOST bits to zero if Rev < C0( = 8).
1199 */
1200 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &revision);
1201 if (revision < C0_1030) {
1202 pci_read_config_byte(pdev, 0x6a, &pcixcmd);
1203 pcixcmd &= 0x8F;
1204 pci_write_config_byte(pdev, 0x6a, pcixcmd);
1205 }
1206 }
1207 else if (pdev->device == MPI_MANUFACTPAGE_DEVID_1030_53C1035) {
1208 ioc->prod_name = "LSI53C1035";
1209 ioc->bus_type = SCSI;
1210 }
1211
1212 if (ioc->errata_flag_1064)
1213 pci_disable_io_access(pdev);
1214
1182 sprintf(ioc->name, "ioc%d", ioc->id);
1183
1184 spin_lock_init(&ioc->FreeQlock);
1185
1186 /* Disable all! */
1187 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
1188 ioc->active = 0;
1189 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);

--- 1472 unchanged lines hidden (view full) ---

2662 return -1;
2663
2664 if (ioc->cached_fw == NULL)
2665 return -2;
2666
2667 /* prevent a second downloadboot and memory free with alt_ioc */
2668 if (ioc->alt_ioc && ioc->alt_ioc->cached_fw)
2669 ioc->alt_ioc->cached_fw = NULL;
1215 sprintf(ioc->name, "ioc%d", ioc->id);
1216
1217 spin_lock_init(&ioc->FreeQlock);
1218
1219 /* Disable all! */
1220 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
1221 ioc->active = 0;
1222 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);

--- 1472 unchanged lines hidden (view full) ---

2695 return -1;
2696
2697 if (ioc->cached_fw == NULL)
2698 return -2;
2699
2700 /* prevent a second downloadboot and memory free with alt_ioc */
2701 if (ioc->alt_ioc && ioc->alt_ioc->cached_fw)
2702 ioc->alt_ioc->cached_fw = NULL;
2670
2703
2671 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
2672 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
2673 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
2674 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
2675 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
2676 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
2677
2678 CHIPREG_WRITE32(&ioc->chip->Diagnostic, (MPI_DIAG_PREVENT_IOC_BOOT | MPI_DIAG_DISABLE_ARM));

--- 41 unchanged lines hidden (view full) ---

2720
2721 pFwHeader = (MpiFwHeader_t *) ioc->cached_fw;
2722 fwSize = (pFwHeader->ImageSize + 3)/4;
2723 ptrFw = (u32 *) pFwHeader;
2724
2725 /* Write the LoadStartAddress to the DiagRw Address Register
2726 * using Programmed IO
2727 */
2704 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
2705 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
2706 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
2707 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
2708 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
2709 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
2710
2711 CHIPREG_WRITE32(&ioc->chip->Diagnostic, (MPI_DIAG_PREVENT_IOC_BOOT | MPI_DIAG_DISABLE_ARM));

--- 41 unchanged lines hidden (view full) ---

2753
2754 pFwHeader = (MpiFwHeader_t *) ioc->cached_fw;
2755 fwSize = (pFwHeader->ImageSize + 3)/4;
2756 ptrFw = (u32 *) pFwHeader;
2757
2758 /* Write the LoadStartAddress to the DiagRw Address Register
2759 * using Programmed IO
2760 */
2761 if (ioc->errata_flag_1064)
2762 pci_enable_io_access(ioc->pcidev);
2763
2728 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, pFwHeader->LoadStartAddress);
2729 ddlprintk((MYIOC_s_INFO_FMT "LoadStart addr written 0x%x \n",
2730 ioc->name, pFwHeader->LoadStartAddress));
2731
2732 ddlprintk((MYIOC_s_INFO_FMT "Write FW Image: 0x%x bytes @ %p\n",
2733 ioc->name, fwSize*4, ptrFw));
2734 while (fwSize--) {
2735 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, *ptrFw++);

--- 30 unchanged lines hidden (view full) ---

2766 * so must do two writes.
2767 */
2768 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, 0x3F000000);
2769 diagRwData = CHIPREG_PIO_READ32(&ioc->pio_chip->DiagRwData);
2770 diagRwData |= 0x4000000;
2771 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, 0x3F000000);
2772 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, diagRwData);
2773
2764 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, pFwHeader->LoadStartAddress);
2765 ddlprintk((MYIOC_s_INFO_FMT "LoadStart addr written 0x%x \n",
2766 ioc->name, pFwHeader->LoadStartAddress));
2767
2768 ddlprintk((MYIOC_s_INFO_FMT "Write FW Image: 0x%x bytes @ %p\n",
2769 ioc->name, fwSize*4, ptrFw));
2770 while (fwSize--) {
2771 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, *ptrFw++);

--- 30 unchanged lines hidden (view full) ---

2802 * so must do two writes.
2803 */
2804 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, 0x3F000000);
2805 diagRwData = CHIPREG_PIO_READ32(&ioc->pio_chip->DiagRwData);
2806 diagRwData |= 0x4000000;
2807 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, 0x3F000000);
2808 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, diagRwData);
2809
2810 if (ioc->errata_flag_1064)
2811 pci_disable_io_access(ioc->pcidev);
2812
2774 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
2775 ddlprintk((MYIOC_s_INFO_FMT "downloadboot diag0val=%x, turning off PREVENT_IOC_BOOT, DISABLE_ARM\n",
2776 ioc->name, diag0val));
2777 diag0val &= ~(MPI_DIAG_PREVENT_IOC_BOOT | MPI_DIAG_DISABLE_ARM);
2778 ddlprintk((MYIOC_s_INFO_FMT "downloadboot now diag0val=%x\n",
2779 ioc->name, diag0val));
2780 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val);
2781

--- 3034 unchanged lines hidden --- 		2813 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
2814 ddlprintk((MYIOC_s_INFO_FMT "downloadboot diag0val=%x, turning off PREVENT_IOC_BOOT, DISABLE_ARM\n",
2815 ioc->name, diag0val));
2816 diag0val &= ~(MPI_DIAG_PREVENT_IOC_BOOT | MPI_DIAG_DISABLE_ARM);
2817 ddlprintk((MYIOC_s_INFO_FMT "downloadboot now diag0val=%x\n",
2818 ioc->name, diag0val));
2819 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val);
2820

--- 3034 unchanged lines hidden ---