max9271.c (ad01032aaf437c526d7135384bb4f998828d0cfc) max9271.c (9e0bf8393d0602cc7fda749b77cf8ec7f81249cb)
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2017-2020 Jacopo Mondi
4 * Copyright (C) 2017-2020 Kieran Bingham
5 * Copyright (C) 2017-2020 Laurent Pinchart
6 * Copyright (C) 2017-2020 Niklas Söderlund
7 * Copyright (C) 2016 Renesas Electronics Corporation
8 * Copyright (C) 2015 Cogent Embedded, Inc.

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75 usleep_range(50, 100);
76 }
77
78 dev_err(&dev->client->dev, "Unable to detect valid pixel clock\n");
79
80 return -EIO;
81}
82
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2017-2020 Jacopo Mondi
4 * Copyright (C) 2017-2020 Kieran Bingham
5 * Copyright (C) 2017-2020 Laurent Pinchart
6 * Copyright (C) 2017-2020 Niklas Söderlund
7 * Copyright (C) 2016 Renesas Electronics Corporation
8 * Copyright (C) 2015 Cogent Embedded, Inc.

--- 66 unchanged lines hidden (view full) ---

75 usleep_range(50, 100);
76 }
77
78 dev_err(&dev->client->dev, "Unable to detect valid pixel clock\n");
79
80 return -EIO;
81}
82
83void max9271_wake_up(struct max9271_device *dev)
84{
85 /*
86 * Use the chip default address as this function has to be called
87 * before any other one.
88 */
89 dev->client->addr = MAX9271_DEFAULT_ADDR;
90 i2c_smbus_read_byte(dev->client);
91 usleep_range(5000, 8000);
92}
93EXPORT_SYMBOL_GPL(max9271_wake_up);
94
83int max9271_set_serial_link(struct max9271_device *dev, bool enable)
84{
85 int ret;
86 u8 val = MAX9271_REVCCEN | MAX9271_FWDCCEN;
87
88 if (enable) {
89 ret = max9271_pclk_detect(dev);
90 if (ret)

--- 272 unchanged lines hidden --- 		95int max9271_set_serial_link(struct max9271_device *dev, bool enable)
96{
97 int ret;
98 u8 val = MAX9271_REVCCEN | MAX9271_FWDCCEN;
99
100 if (enable) {
101 ret = max9271_pclk_detect(dev);
102 if (ret)

--- 272 unchanged lines hidden ---