| ccs-pll.c (482e75e7b3eba6730cbfaa1911916d13887c9606) | ccs-pll.c (c64cf71d10c36513071ca538f59e4c38eb25ae55) |
|---|---|
| 1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * drivers/media/i2c/ccs-pll.c 4 * 5 * Generic MIPI CCS/SMIA/SMIA++ PLL calculator 6 * 7 * Copyright (C) 2020 Intel Corporation 8 * Copyright (C) 2011--2012 Nokia Corporation --- 189 unchanged lines hidden (view full) --- 198 dev_dbg(dev, "more_mul_max: max_pll_op_clk_freq_hz check: %u\n", 199 more_mul_max); 200 /* Don't go above the division capability of op sys clock divider. */ 201 more_mul_max = min(more_mul_max, 202 op_lim_bk->max_sys_clk_div * op_pll_fr->pre_pll_clk_div 203 / div); 204 dev_dbg(dev, "more_mul_max: max_op_sys_clk_div check: %u\n", 205 more_mul_max); | 1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * drivers/media/i2c/ccs-pll.c 4 * 5 * Generic MIPI CCS/SMIA/SMIA++ PLL calculator 6 * 7 * Copyright (C) 2020 Intel Corporation 8 * Copyright (C) 2011--2012 Nokia Corporation --- 189 unchanged lines hidden (view full) --- 198 dev_dbg(dev, "more_mul_max: max_pll_op_clk_freq_hz check: %u\n", 199 more_mul_max); 200 /* Don't go above the division capability of op sys clock divider. */ 201 more_mul_max = min(more_mul_max, 202 op_lim_bk->max_sys_clk_div * op_pll_fr->pre_pll_clk_div 203 / div); 204 dev_dbg(dev, "more_mul_max: max_op_sys_clk_div check: %u\n", 205 more_mul_max); |
| 206 /* Ensure we won't go above min_pll_multiplier. */ | 206 /* Ensure we won't go above max_pll_multiplier. */ |
| 207 more_mul_max = min(more_mul_max, 208 DIV_ROUND_UP(op_lim_fr->max_pll_multiplier, mul)); 209 dev_dbg(dev, "more_mul_max: min_pll_multiplier check: %u\n", 210 more_mul_max); 211 212 /* Ensure we won't go below min_pll_op_clk_freq_hz. */ 213 more_mul_min = DIV_ROUND_UP(op_lim_fr->min_pll_op_clk_freq_hz, 214 pll->ext_clk_freq_hz / --- 280 unchanged lines hidden --- | 207 more_mul_max = min(more_mul_max, 208 DIV_ROUND_UP(op_lim_fr->max_pll_multiplier, mul)); 209 dev_dbg(dev, "more_mul_max: min_pll_multiplier check: %u\n", 210 more_mul_max); 211 212 /* Ensure we won't go below min_pll_op_clk_freq_hz. */ 213 more_mul_min = DIV_ROUND_UP(op_lim_fr->min_pll_op_clk_freq_hz, 214 pll->ext_clk_freq_hz / --- 280 unchanged lines hidden --- |