mISDNinfineon.c (239060b93bb30a4ad55f1ecaa512464a035cc5ba) | mISDNinfineon.c (4101e976e0376a1820ae55adf8bca7dda5089a7d) |
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1/* 2 * mISDNinfineon.c 3 * Support for cards based on following Infineon ISDN chipsets 4 * - ISAC + HSCX 5 * - IPAC and IPAC-X 6 * - ISAC-SX + HSCX 7 * 8 * Supported cards: --- 549 unchanged lines hidden (view full) --- 558 val |= (GAZEL_RESET_9050 + GAZEL_RESET); 559 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL); 560 val &= ~(GAZEL_RESET_9050 + GAZEL_RESET); 561 mdelay(4); 562 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL); 563 mdelay(10); 564 hw->ipac.isac.adf2 = 0x87; 565 hw->ipac.hscx[0].slot = 0x1f; | 1/* 2 * mISDNinfineon.c 3 * Support for cards based on following Infineon ISDN chipsets 4 * - ISAC + HSCX 5 * - IPAC and IPAC-X 6 * - ISAC-SX + HSCX 7 * 8 * Supported cards: --- 549 unchanged lines hidden (view full) --- 558 val |= (GAZEL_RESET_9050 + GAZEL_RESET); 559 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL); 560 val &= ~(GAZEL_RESET_9050 + GAZEL_RESET); 561 mdelay(4); 562 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL); 563 mdelay(10); 564 hw->ipac.isac.adf2 = 0x87; 565 hw->ipac.hscx[0].slot = 0x1f; |
566 hw->ipac.hscx[0].slot = 0x23; | 566 hw->ipac.hscx[1].slot = 0x23; |
567 break; 568 case INF_GAZEL_R753: 569 val = inl((u32)hw->cfg.start + GAZEL_CNTRL); 570 val |= (GAZEL_RESET_9050 + GAZEL_RESET); 571 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL); 572 val &= ~(GAZEL_RESET_9050 + GAZEL_RESET); 573 mdelay(4); 574 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL); --- 598 unchanged lines hidden --- | 567 break; 568 case INF_GAZEL_R753: 569 val = inl((u32)hw->cfg.start + GAZEL_CNTRL); 570 val |= (GAZEL_RESET_9050 + GAZEL_RESET); 571 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL); 572 val &= ~(GAZEL_RESET_9050 + GAZEL_RESET); 573 mdelay(4); 574 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL); --- 598 unchanged lines hidden --- |