| ipmmu-vmsa.c (e27a24210aa17b8a0cd462865130fe73afd7e001) | ipmmu-vmsa.c (298f78895b081911e0b3605f07d79ebd3d4cf7b0) |
|---|---|
| 1// SPDX-License-Identifier: GPL-2.0 2/* 3 * IOMMU API for Renesas VMSA-compatible IPMMU 4 * Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com> 5 * 6 * Copyright (C) 2014 Renesas Electronics Corporation 7 */ 8 --- 353 unchanged lines hidden (view full) --- 362} 363 364static void ipmmu_tlb_add_flush(unsigned long iova, size_t size, 365 size_t granule, bool leaf, void *cookie) 366{ 367 /* The hardware doesn't support selective TLB flush. */ 368} 369 | 1// SPDX-License-Identifier: GPL-2.0 2/* 3 * IOMMU API for Renesas VMSA-compatible IPMMU 4 * Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com> 5 * 6 * Copyright (C) 2014 Renesas Electronics Corporation 7 */ 8 --- 353 unchanged lines hidden (view full) --- 362} 363 364static void ipmmu_tlb_add_flush(unsigned long iova, size_t size, 365 size_t granule, bool leaf, void *cookie) 366{ 367 /* The hardware doesn't support selective TLB flush. */ 368} 369 |
| 370static const struct iommu_gather_ops ipmmu_gather_ops = { | 370static const struct iommu_flush_ops ipmmu_flush_ops = { |
| 371 .tlb_flush_all = ipmmu_tlb_flush_all, 372 .tlb_add_flush = ipmmu_tlb_add_flush, 373 .tlb_sync = ipmmu_tlb_flush_all, 374}; 375 376/* ----------------------------------------------------------------------------- 377 * Domain/Context Management 378 */ --- 96 unchanged lines hidden (view full) --- 475 * not to comply with this, as it generates a secure access page fault 476 * if any of the NStable and NS bits isn't set when running in 477 * non-secure mode. 478 */ 479 domain->cfg.quirks = IO_PGTABLE_QUIRK_ARM_NS; 480 domain->cfg.pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K; 481 domain->cfg.ias = 32; 482 domain->cfg.oas = 40; | 371 .tlb_flush_all = ipmmu_tlb_flush_all, 372 .tlb_add_flush = ipmmu_tlb_add_flush, 373 .tlb_sync = ipmmu_tlb_flush_all, 374}; 375 376/* ----------------------------------------------------------------------------- 377 * Domain/Context Management 378 */ --- 96 unchanged lines hidden (view full) --- 475 * not to comply with this, as it generates a secure access page fault 476 * if any of the NStable and NS bits isn't set when running in 477 * non-secure mode. 478 */ 479 domain->cfg.quirks = IO_PGTABLE_QUIRK_ARM_NS; 480 domain->cfg.pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K; 481 domain->cfg.ias = 32; 482 domain->cfg.oas = 40; |
| 483 domain->cfg.tlb = &ipmmu_gather_ops; | 483 domain->cfg.tlb = &ipmmu_flush_ops; |
| 484 domain->io_domain.geometry.aperture_end = DMA_BIT_MASK(32); 485 domain->io_domain.geometry.force_aperture = true; 486 /* 487 * TODO: Add support for coherent walk through CCI with DVM and remove 488 * cache handling. For now, delegate it to the io-pgtable code. 489 */ 490 domain->cfg.coherent_walk = false; 491 domain->cfg.iommu_dev = domain->mmu->root->dev; --- 752 unchanged lines hidden --- | 484 domain->io_domain.geometry.aperture_end = DMA_BIT_MASK(32); 485 domain->io_domain.geometry.force_aperture = true; 486 /* 487 * TODO: Add support for coherent walk through CCI with DVM and remove 488 * cache handling. For now, delegate it to the io-pgtable code. 489 */ 490 domain->cfg.coherent_walk = false; 491 domain->cfg.iommu_dev = domain->mmu->root->dev; --- 752 unchanged lines hidden --- |