init.c (c69d89aff393a212b9635c95990173b48d8bd74d) init.c (54ce12e02e44feffa6de4f3a069b7d5c7262a966)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 * Leo Duran <leo.duran@amd.com>
6 */
7
8#define pr_fmt(fmt) "AMD-Vi: " fmt

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354 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
355 &entry, sizeof(entry));
356
357 entry = limit;
358 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
359 &entry, sizeof(entry));
360}
361
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 * Leo Duran <leo.duran@amd.com>
6 */
7
8#define pr_fmt(fmt) "AMD-Vi: " fmt

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354 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
355 &entry, sizeof(entry));
356
357 entry = limit;
358 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
359 &entry, sizeof(entry));
360}
361
362static void iommu_set_cwwb_range(struct amd_iommu *iommu)
363{
364 u64 start = iommu_virt_to_phys((void *)iommu->cmd_sem);
365 u64 entry = start & PM_ADDR_MASK;
366
367 if (!iommu_feature(iommu, FEATURE_SNP))
368 return;
369
370 /* Note:
371 * Re-purpose Exclusion base/limit registers for Completion wait
372 * write-back base/limit.
373 */
374 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
375 &entry, sizeof(entry));
376
377 /* Note:
378 * Default to 4 Kbytes, which can be specified by setting base
379 * address equal to the limit address.
380 */
381 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
382 &entry, sizeof(entry));
383}
384
362/* Programs the physical address of the device table into the IOMMU hardware */
363static void iommu_set_device_table(struct amd_iommu *iommu)
364{
365 u64 entry;
366
367 BUG_ON(iommu->mmio_base == NULL);
368
369 entry = iommu_virt_to_phys(amd_iommu_dev_table);

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1879{
1880 struct amd_iommu *iommu;
1881 int ret = 0;
1882
1883 for_each_iommu(iommu) {
1884 ret = iommu_init_pci(iommu);
1885 if (ret)
1886 break;
385/* Programs the physical address of the device table into the IOMMU hardware */
386static void iommu_set_device_table(struct amd_iommu *iommu)
387{
388 u64 entry;
389
390 BUG_ON(iommu->mmio_base == NULL);
391
392 entry = iommu_virt_to_phys(amd_iommu_dev_table);

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1902{
1903 struct amd_iommu *iommu;
1904 int ret = 0;
1905
1906 for_each_iommu(iommu) {
1907 ret = iommu_init_pci(iommu);
1908 if (ret)
1909 break;
1910
1911 /* Need to setup range after PCI init */
1912 iommu_set_cwwb_range(iommu);
1887 }
1888
1889 /*
1890 * Order is important here to make sure any unity map requirements are
1891 * fulfilled. The unity mappings are created and written to the device
1892 * table during the amd_iommu_init_api() call.
1893 *
1894 * After that we call init_device_table_dma() to make sure any

--- 1291 unchanged lines hidden --- 		1913 }
1914
1915 /*
1916 * Order is important here to make sure any unity map requirements are
1917 * fulfilled. The unity mappings are created and written to the device
1918 * table during the amd_iommu_init_api() call.
1919 *
1920 * After that we call init_device_table_dma() to make sure any

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