init.c (be227f8e99a663d097536e9f9bc935fb26bdbc41) init.c (b65412c25fa600d8a4085e820bdfadb9d9bab6b9)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 * Leo Duran <leo.duran@amd.com>
6 */
7
8#define pr_fmt(fmt) "AMD-Vi: " fmt

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148bool amd_iommu_irq_remap __read_mostly;
149
150enum io_pgtable_fmt amd_iommu_pgtable = AMD_IOMMU_V1;
151
152int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
153static int amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE;
154
155static bool amd_iommu_detected;
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 * Leo Duran <leo.duran@amd.com>
6 */
7
8#define pr_fmt(fmt) "AMD-Vi: " fmt

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148bool amd_iommu_irq_remap __read_mostly;
149
150enum io_pgtable_fmt amd_iommu_pgtable = AMD_IOMMU_V1;
151
152int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
153static int amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE;
154
155static bool amd_iommu_detected;
156static bool __initdata amd_iommu_disabled;
156static bool amd_iommu_disabled __initdata;
157static bool amd_iommu_force_enable __initdata;
157static int amd_iommu_target_ivhd_type;
158
159u16 amd_iommu_last_bdf; /* largest PCI device id we have
160 to handle */
161LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
162 we find in ACPI */
163bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
164

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226
227enum iommu_init_state {
228 IOMMU_START_STATE,
229 IOMMU_IVRS_DETECTED,
230 IOMMU_ACPI_FINISHED,
231 IOMMU_ENABLED,
232 IOMMU_PCI_INIT,
233 IOMMU_INTERRUPTS_EN,
158static int amd_iommu_target_ivhd_type;
159
160u16 amd_iommu_last_bdf; /* largest PCI device id we have
161 to handle */
162LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
163 we find in ACPI */
164bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
165

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227
228enum iommu_init_state {
229 IOMMU_START_STATE,
230 IOMMU_IVRS_DETECTED,
231 IOMMU_ACPI_FINISHED,
232 IOMMU_ENABLED,
233 IOMMU_PCI_INIT,
234 IOMMU_INTERRUPTS_EN,
235 IOMMU_DMA_OPS,
234 IOMMU_INITIALIZED,
235 IOMMU_NOT_FOUND,
236 IOMMU_INIT_ERROR,
237 IOMMU_CMDLINE_DISABLED,
238};
239
240/* Early ioapic and hpet maps from kernel command line */
241#define EARLY_MAP_SIZE 4

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1902
1903 for_each_iommu(iommu) {
1904 struct pci_dev *pdev = iommu->dev;
1905 int i;
1906
1907 pci_info(pdev, "Found IOMMU cap 0x%x\n", iommu->cap_ptr);
1908
1909 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
236 IOMMU_INITIALIZED,
237 IOMMU_NOT_FOUND,
238 IOMMU_INIT_ERROR,
239 IOMMU_CMDLINE_DISABLED,
240};
241
242/* Early ioapic and hpet maps from kernel command line */
243#define EARLY_MAP_SIZE 4

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1904
1905 for_each_iommu(iommu) {
1906 struct pci_dev *pdev = iommu->dev;
1907 int i;
1908
1909 pci_info(pdev, "Found IOMMU cap 0x%x\n", iommu->cap_ptr);
1910
1911 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
1910 pci_info(pdev, "Extended features (%#llx):",
1911 iommu->features);
1912 pr_info("Extended features (%#llx):", iommu->features);
1913
1912 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) {
1913 if (iommu_feature(iommu, (1ULL << i)))
1914 pr_cont(" %s", feat_str[i]);
1915 }
1916
1917 if (iommu->features & FEATURE_GAM_VAPIC)
1918 pr_cont(" GA_vAPIC");
1919

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2811 if (ret)
2812 goto out;
2813 }
2814
2815out:
2816 return ret;
2817}
2818
1914 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) {
1915 if (iommu_feature(iommu, (1ULL << i)))
1916 pr_cont(" %s", feat_str[i]);
1917 }
1918
1919 if (iommu->features & FEATURE_GAM_VAPIC)
1920 pr_cont(" GA_vAPIC");
1921

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2813 if (ret)
2814 goto out;
2815 }
2816
2817out:
2818 return ret;
2819}
2820
2819static bool detect_ivrs(void)
2821static bool __init detect_ivrs(void)
2820{
2821 struct acpi_table_header *ivrs_base;
2822 acpi_status status;
2823 int i;
2824
2825 status = acpi_get_table("IVRS", 0, &ivrs_base);
2826 if (status == AE_NOT_FOUND)
2827 return false;
2828 else if (ACPI_FAILURE(status)) {
2829 const char *err = acpi_format_exception(status);
2830 pr_err("IVRS table error: %s\n", err);
2831 return false;
2832 }
2833
2834 acpi_put_table(ivrs_base);
2835
2822{
2823 struct acpi_table_header *ivrs_base;
2824 acpi_status status;
2825 int i;
2826
2827 status = acpi_get_table("IVRS", 0, &ivrs_base);
2828 if (status == AE_NOT_FOUND)
2829 return false;
2830 else if (ACPI_FAILURE(status)) {
2831 const char *err = acpi_format_exception(status);
2832 pr_err("IVRS table error: %s\n", err);
2833 return false;
2834 }
2835
2836 acpi_put_table(ivrs_base);
2837
2838 if (amd_iommu_force_enable)
2839 goto out;
2840
2836 /* Don't use IOMMU if there is Stoney Ridge graphics */
2837 for (i = 0; i < 32; i++) {
2838 u32 pci_id;
2839
2840 pci_id = read_pci_config(0, i, 0, 0);
2841 if ((pci_id & 0xffff) == 0x1002 && (pci_id >> 16) == 0x98e4) {
2842 pr_info("Disable IOMMU on Stoney Ridge\n");
2843 return false;
2844 }
2845 }
2846
2841 /* Don't use IOMMU if there is Stoney Ridge graphics */
2842 for (i = 0; i < 32; i++) {
2843 u32 pci_id;
2844
2845 pci_id = read_pci_config(0, i, 0, 0);
2846 if ((pci_id & 0xffff) == 0x1002 && (pci_id >> 16) == 0x98e4) {
2847 pr_info("Disable IOMMU on Stoney Ridge\n");
2848 return false;
2849 }
2850 }
2851
2852out:
2847 /* Make sure ACS will be enabled during PCI probe */
2848 pci_request_acs();
2849
2850 return true;
2851}
2852
2853/****************************************************************************
2854 *

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2889 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT;
2890 enable_iommus_v2();
2891 break;
2892 case IOMMU_PCI_INIT:
2893 ret = amd_iommu_enable_interrupts();
2894 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN;
2895 break;
2896 case IOMMU_INTERRUPTS_EN:
2853 /* Make sure ACS will be enabled during PCI probe */
2854 pci_request_acs();
2855
2856 return true;
2857}
2858
2859/****************************************************************************
2860 *

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2895 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT;
2896 enable_iommus_v2();
2897 break;
2898 case IOMMU_PCI_INIT:
2899 ret = amd_iommu_enable_interrupts();
2900 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN;
2901 break;
2902 case IOMMU_INTERRUPTS_EN:
2903 ret = amd_iommu_init_dma_ops();
2904 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS;
2905 break;
2906 case IOMMU_DMA_OPS:
2897 init_state = IOMMU_INITIALIZED;
2898 break;
2899 case IOMMU_INITIALIZED:
2900 /* Nothing to do */
2901 break;
2902 case IOMMU_NOT_FOUND:
2903 case IOMMU_INIT_ERROR:
2904 case IOMMU_CMDLINE_DISABLED:

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3090 return 1;
3091}
3092
3093static int __init parse_amd_iommu_options(char *str)
3094{
3095 for (; *str; ++str) {
3096 if (strncmp(str, "fullflush", 9) == 0)
3097 amd_iommu_unmap_flush = true;
2907 init_state = IOMMU_INITIALIZED;
2908 break;
2909 case IOMMU_INITIALIZED:
2910 /* Nothing to do */
2911 break;
2912 case IOMMU_NOT_FOUND:
2913 case IOMMU_INIT_ERROR:
2914 case IOMMU_CMDLINE_DISABLED:

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3100 return 1;
3101}
3102
3103static int __init parse_amd_iommu_options(char *str)
3104{
3105 for (; *str; ++str) {
3106 if (strncmp(str, "fullflush", 9) == 0)
3107 amd_iommu_unmap_flush = true;
3108 if (strncmp(str, "force_enable", 12) == 0)
3109 amd_iommu_force_enable = true;
3098 if (strncmp(str, "off", 3) == 0)
3099 amd_iommu_disabled = true;
3100 if (strncmp(str, "force_isolation", 15) == 0)
3101 amd_iommu_force_isolation = true;
3102 }
3103
3104 return 1;
3105}

--- 210 unchanged lines hidden --- 		3110 if (strncmp(str, "off", 3) == 0)
3111 amd_iommu_disabled = true;
3112 if (strncmp(str, "force_isolation", 15) == 0)
3113 amd_iommu_force_isolation = true;
3114 }
3115
3116 return 1;
3117}

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