init.c (6bde8ef51c917a657476310728d6cb3de6bac9e4) | init.c (06ce8a62ce81f47542043d93b64a4be106e98106) |
---|---|
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. 4 * Author: Joerg Roedel <jroedel@suse.de> 5 * Leo Duran <leo.duran@amd.com> 6 */ 7 8#define pr_fmt(fmt) "AMD-Vi: " fmt --- 1564 unchanged lines hidden (view full) --- 1573 */ 1574 amd_iommu_rlookup_table[iommu->devid] = NULL; 1575 1576 return 0; 1577} 1578 1579/** 1580 * get_highest_supported_ivhd_type - Look up the appropriate IVHD type | 1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. 4 * Author: Joerg Roedel <jroedel@suse.de> 5 * Leo Duran <leo.duran@amd.com> 6 */ 7 8#define pr_fmt(fmt) "AMD-Vi: " fmt --- 1564 unchanged lines hidden (view full) --- 1573 */ 1574 amd_iommu_rlookup_table[iommu->devid] = NULL; 1575 1576 return 0; 1577} 1578 1579/** 1580 * get_highest_supported_ivhd_type - Look up the appropriate IVHD type |
1581 * @ivrs Pointer to the IVRS header | 1581 * @ivrs: Pointer to the IVRS header |
1582 * 1583 * This function search through all IVDB of the maximum supported IVHD 1584 */ 1585static u8 get_highest_supported_ivhd_type(struct acpi_table_header *ivrs) 1586{ 1587 u8 *base = (u8 *)ivrs; 1588 struct ivhd_header *ivhd = (struct ivhd_header *) 1589 (base + IVRS_HEADER_LENGTH); --- 334 unchanged lines hidden (view full) --- 1924 return 0; 1925} 1926 1927#define XT_INT_DEST_MODE(x) (((x) & 0x1ULL) << 2) 1928#define XT_INT_DEST_LO(x) (((x) & 0xFFFFFFULL) << 8) 1929#define XT_INT_VEC(x) (((x) & 0xFFULL) << 32) 1930#define XT_INT_DEST_HI(x) ((((x) >> 24) & 0xFFULL) << 56) 1931 | 1582 * 1583 * This function search through all IVDB of the maximum supported IVHD 1584 */ 1585static u8 get_highest_supported_ivhd_type(struct acpi_table_header *ivrs) 1586{ 1587 u8 *base = (u8 *)ivrs; 1588 struct ivhd_header *ivhd = (struct ivhd_header *) 1589 (base + IVRS_HEADER_LENGTH); --- 334 unchanged lines hidden (view full) --- 1924 return 0; 1925} 1926 1927#define XT_INT_DEST_MODE(x) (((x) & 0x1ULL) << 2) 1928#define XT_INT_DEST_LO(x) (((x) & 0xFFFFFFULL) << 8) 1929#define XT_INT_VEC(x) (((x) & 0xFFULL) << 32) 1930#define XT_INT_DEST_HI(x) ((((x) >> 24) & 0xFFULL) << 56) 1931 |
1932/** | 1932/* |
1933 * Setup the IntCapXT registers with interrupt routing information 1934 * based on the PCI MSI capability block registers, accessed via 1935 * MMIO MSI address low/hi and MSI data registers. 1936 */ 1937static void iommu_update_intcapxt(struct amd_iommu *iommu) 1938{ 1939 u64 val; 1940 u32 addr_lo = readl(iommu->mmio_base + MMIO_MSI_ADDR_LO_OFFSET); --- 312 unchanged lines hidden (view full) --- 2253} 2254 2255static void iommu_enable_ga(struct amd_iommu *iommu) 2256{ 2257#ifdef CONFIG_IRQ_REMAP 2258 switch (amd_iommu_guest_ir) { 2259 case AMD_IOMMU_GUEST_IR_VAPIC: 2260 iommu_feature_enable(iommu, CONTROL_GAM_EN); | 1933 * Setup the IntCapXT registers with interrupt routing information 1934 * based on the PCI MSI capability block registers, accessed via 1935 * MMIO MSI address low/hi and MSI data registers. 1936 */ 1937static void iommu_update_intcapxt(struct amd_iommu *iommu) 1938{ 1939 u64 val; 1940 u32 addr_lo = readl(iommu->mmio_base + MMIO_MSI_ADDR_LO_OFFSET); --- 312 unchanged lines hidden (view full) --- 2253} 2254 2255static void iommu_enable_ga(struct amd_iommu *iommu) 2256{ 2257#ifdef CONFIG_IRQ_REMAP 2258 switch (amd_iommu_guest_ir) { 2259 case AMD_IOMMU_GUEST_IR_VAPIC: 2260 iommu_feature_enable(iommu, CONTROL_GAM_EN); |
2261 /* Fall through */ | 2261 fallthrough; |
2262 case AMD_IOMMU_GUEST_IR_LEGACY_GA: 2263 iommu_feature_enable(iommu, CONTROL_GA_EN); 2264 iommu->irte_ops = &irte_128_ops; 2265 break; 2266 default: 2267 iommu->irte_ops = &irte_32_ops; 2268 break; 2269 } --- 898 unchanged lines hidden --- | 2262 case AMD_IOMMU_GUEST_IR_LEGACY_GA: 2263 iommu_feature_enable(iommu, CONTROL_GA_EN); 2264 iommu->irte_ops = &irte_128_ops; 2265 break; 2266 default: 2267 iommu->irte_ops = &irte_32_ops; 2268 break; 2269 } --- 898 unchanged lines hidden --- |