init.c (320424c7d44f54c18df9812fd7c45f6963524002) init.c (1d479f160c500249d8fa4d21e7d2b7aaffc04daf)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 * Leo Duran <leo.duran@amd.com>
6 */
7
8#define pr_fmt(fmt) "AMD-Vi: " fmt

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148bool amd_iommu_irq_remap __read_mostly;
149
150enum io_pgtable_fmt amd_iommu_pgtable = AMD_IOMMU_V1;
151
152int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
153static int amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE;
154
155static bool amd_iommu_detected;
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 * Leo Duran <leo.duran@amd.com>
6 */
7
8#define pr_fmt(fmt) "AMD-Vi: " fmt

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148bool amd_iommu_irq_remap __read_mostly;
149
150enum io_pgtable_fmt amd_iommu_pgtable = AMD_IOMMU_V1;
151
152int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
153static int amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE;
154
155static bool amd_iommu_detected;
156static bool __initdata amd_iommu_disabled;
156static bool amd_iommu_disabled __initdata;
157static bool amd_iommu_force_enable __initdata;
157static int amd_iommu_target_ivhd_type;
158
159u16 amd_iommu_last_bdf; /* largest PCI device id we have
160 to handle */
161LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
162 we find in ACPI */
163bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
164

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226
227enum iommu_init_state {
228 IOMMU_START_STATE,
229 IOMMU_IVRS_DETECTED,
230 IOMMU_ACPI_FINISHED,
231 IOMMU_ENABLED,
232 IOMMU_PCI_INIT,
233 IOMMU_INTERRUPTS_EN,
158static int amd_iommu_target_ivhd_type;
159
160u16 amd_iommu_last_bdf; /* largest PCI device id we have
161 to handle */
162LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
163 we find in ACPI */
164bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
165

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227
228enum iommu_init_state {
229 IOMMU_START_STATE,
230 IOMMU_IVRS_DETECTED,
231 IOMMU_ACPI_FINISHED,
232 IOMMU_ENABLED,
233 IOMMU_PCI_INIT,
234 IOMMU_INTERRUPTS_EN,
234 IOMMU_DMA_OPS,
235 IOMMU_INITIALIZED,
236 IOMMU_NOT_FOUND,
237 IOMMU_INIT_ERROR,
238 IOMMU_CMDLINE_DISABLED,
239};
240
241/* Early ioapic and hpet maps from kernel command line */
242#define EARLY_MAP_SIZE 4

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1903
1904 for_each_iommu(iommu) {
1905 struct pci_dev *pdev = iommu->dev;
1906 int i;
1907
1908 pci_info(pdev, "Found IOMMU cap 0x%x\n", iommu->cap_ptr);
1909
1910 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
235 IOMMU_INITIALIZED,
236 IOMMU_NOT_FOUND,
237 IOMMU_INIT_ERROR,
238 IOMMU_CMDLINE_DISABLED,
239};
240
241/* Early ioapic and hpet maps from kernel command line */
242#define EARLY_MAP_SIZE 4

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1903
1904 for_each_iommu(iommu) {
1905 struct pci_dev *pdev = iommu->dev;
1906 int i;
1907
1908 pci_info(pdev, "Found IOMMU cap 0x%x\n", iommu->cap_ptr);
1909
1910 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
1911 pci_info(pdev, "Extended features (%#llx):",
1912 iommu->features);
1911 pr_info("Extended features (%#llx):", iommu->features);
1912
1913 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) {
1914 if (iommu_feature(iommu, (1ULL << i)))
1915 pr_cont(" %s", feat_str[i]);
1916 }
1917
1918 if (iommu->features & FEATURE_GAM_VAPIC)
1919 pr_cont(" GA_vAPIC");
1920

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2812 if (ret)
2813 goto out;
2814 }
2815
2816out:
2817 return ret;
2818}
2819
1913 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) {
1914 if (iommu_feature(iommu, (1ULL << i)))
1915 pr_cont(" %s", feat_str[i]);
1916 }
1917
1918 if (iommu->features & FEATURE_GAM_VAPIC)
1919 pr_cont(" GA_vAPIC");
1920

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2812 if (ret)
2813 goto out;
2814 }
2815
2816out:
2817 return ret;
2818}
2819
2820static bool detect_ivrs(void)
2820static bool __init detect_ivrs(void)
2821{
2822 struct acpi_table_header *ivrs_base;
2823 acpi_status status;
2824 int i;
2825
2826 status = acpi_get_table("IVRS", 0, &ivrs_base);
2827 if (status == AE_NOT_FOUND)
2828 return false;
2829 else if (ACPI_FAILURE(status)) {
2830 const char *err = acpi_format_exception(status);
2831 pr_err("IVRS table error: %s\n", err);
2832 return false;
2833 }
2834
2835 acpi_put_table(ivrs_base);
2836
2821{
2822 struct acpi_table_header *ivrs_base;
2823 acpi_status status;
2824 int i;
2825
2826 status = acpi_get_table("IVRS", 0, &ivrs_base);
2827 if (status == AE_NOT_FOUND)
2828 return false;
2829 else if (ACPI_FAILURE(status)) {
2830 const char *err = acpi_format_exception(status);
2831 pr_err("IVRS table error: %s\n", err);
2832 return false;
2833 }
2834
2835 acpi_put_table(ivrs_base);
2836
2837 if (amd_iommu_force_enable)
2838 goto out;
2839
2837 /* Don't use IOMMU if there is Stoney Ridge graphics */
2838 for (i = 0; i < 32; i++) {
2839 u32 pci_id;
2840
2841 pci_id = read_pci_config(0, i, 0, 0);
2842 if ((pci_id & 0xffff) == 0x1002 && (pci_id >> 16) == 0x98e4) {
2843 pr_info("Disable IOMMU on Stoney Ridge\n");
2844 return false;
2845 }
2846 }
2847
2840 /* Don't use IOMMU if there is Stoney Ridge graphics */
2841 for (i = 0; i < 32; i++) {
2842 u32 pci_id;
2843
2844 pci_id = read_pci_config(0, i, 0, 0);
2845 if ((pci_id & 0xffff) == 0x1002 && (pci_id >> 16) == 0x98e4) {
2846 pr_info("Disable IOMMU on Stoney Ridge\n");
2847 return false;
2848 }
2849 }
2850
2851out:
2848 /* Make sure ACS will be enabled during PCI probe */
2849 pci_request_acs();
2850
2851 return true;
2852}
2853
2854/****************************************************************************
2855 *

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2890 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT;
2891 enable_iommus_v2();
2892 break;
2893 case IOMMU_PCI_INIT:
2894 ret = amd_iommu_enable_interrupts();
2895 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN;
2896 break;
2897 case IOMMU_INTERRUPTS_EN:
2852 /* Make sure ACS will be enabled during PCI probe */
2853 pci_request_acs();
2854
2855 return true;
2856}
2857
2858/****************************************************************************
2859 *

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2894 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT;
2895 enable_iommus_v2();
2896 break;
2897 case IOMMU_PCI_INIT:
2898 ret = amd_iommu_enable_interrupts();
2899 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN;
2900 break;
2901 case IOMMU_INTERRUPTS_EN:
2898 ret = amd_iommu_init_dma_ops();
2899 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS;
2900 break;
2901 case IOMMU_DMA_OPS:
2902 init_state = IOMMU_INITIALIZED;
2903 break;
2904 case IOMMU_INITIALIZED:
2905 /* Nothing to do */
2906 break;
2907 case IOMMU_NOT_FOUND:
2908 case IOMMU_INIT_ERROR:
2909 case IOMMU_CMDLINE_DISABLED:

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3093 }
3094 }
3095 return 1;
3096}
3097
3098static int __init parse_amd_iommu_options(char *str)
3099{
3100 for (; *str; ++str) {
2902 init_state = IOMMU_INITIALIZED;
2903 break;
2904 case IOMMU_INITIALIZED:
2905 /* Nothing to do */
2906 break;
2907 case IOMMU_NOT_FOUND:
2908 case IOMMU_INIT_ERROR:
2909 case IOMMU_CMDLINE_DISABLED:

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3093 }
3094 }
3095 return 1;
3096}
3097
3098static int __init parse_amd_iommu_options(char *str)
3099{
3100 for (; *str; ++str) {
3101 if (strncmp(str, "fullflush", 9) == 0)
3101 if (strncmp(str, "fullflush", 9) == 0) {
3102 pr_warn("amd_iommu=fullflush deprecated; use iommu.strict=1 instead\n");
3102 amd_iommu_unmap_flush = true;
3103 amd_iommu_unmap_flush = true;
3104 }
3105 if (strncmp(str, "force_enable", 12) == 0)
3106 amd_iommu_force_enable = true;
3103 if (strncmp(str, "off", 3) == 0)
3104 amd_iommu_disabled = true;
3105 if (strncmp(str, "force_isolation", 15) == 0)
3106 amd_iommu_force_isolation = true;
3107 }
3108
3109 return 1;
3110}

--- 210 unchanged lines hidden --- 		3107 if (strncmp(str, "off", 3) == 0)
3108 amd_iommu_disabled = true;
3109 if (strncmp(str, "force_isolation", 15) == 0)
3110 amd_iommu_force_isolation = true;
3111 }
3112
3113 return 1;
3114}

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