| init.c (02c6f31d0e010a7eef849ca6457e5801de2b42d1) | init.c (fb2accadaa9427a374fa9f482ea24ca731f675ba) |
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| 1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. 4 * Author: Joerg Roedel <jroedel@suse.de> 5 * Leo Duran <leo.duran@amd.com> 6 */ 7 8#define pr_fmt(fmt) "AMD-Vi: " fmt --- 154 unchanged lines hidden (view full) --- 163static bool amd_iommu_disabled __initdata; 164static bool amd_iommu_force_enable __initdata; 165static int amd_iommu_target_ivhd_type; 166 167/* Global EFR and EFR2 registers */ 168u64 amd_iommu_efr; 169u64 amd_iommu_efr2; 170 | 1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. 4 * Author: Joerg Roedel <jroedel@suse.de> 5 * Leo Duran <leo.duran@amd.com> 6 */ 7 8#define pr_fmt(fmt) "AMD-Vi: " fmt --- 154 unchanged lines hidden (view full) --- 163static bool amd_iommu_disabled __initdata; 164static bool amd_iommu_force_enable __initdata; 165static int amd_iommu_target_ivhd_type; 166 167/* Global EFR and EFR2 registers */ 168u64 amd_iommu_efr; 169u64 amd_iommu_efr2; 170 |
| 171/* SNP is enabled on the system? */ 172bool amd_iommu_snp_en; 173EXPORT_SYMBOL(amd_iommu_snp_en); 174 |
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| 171LIST_HEAD(amd_iommu_pci_seg_list); /* list of all PCI segments */ 172LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the 173 system */ 174 175/* Array to assign indices to IOMMUs*/ 176struct amd_iommu *amd_iommus[MAX_IOMMUS]; 177 178/* Number of IOMMUs present in the system */ --- 3372 unchanged lines hidden (view full) --- 3551 3552int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) 3553{ 3554 if (!iommu) 3555 return -EINVAL; 3556 3557 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true); 3558} | 175LIST_HEAD(amd_iommu_pci_seg_list); /* list of all PCI segments */ 176LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the 177 system */ 178 179/* Array to assign indices to IOMMUs*/ 180struct amd_iommu *amd_iommus[MAX_IOMMUS]; 181 182/* Number of IOMMUs present in the system */ --- 3372 unchanged lines hidden (view full) --- 3555 3556int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) 3557{ 3558 if (!iommu) 3559 return -EINVAL; 3560 3561 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true); 3562} |
| 3563 3564#ifdef CONFIG_AMD_MEM_ENCRYPT 3565int amd_iommu_snp_enable(void) 3566{ 3567 /* 3568 * The SNP support requires that IOMMU must be enabled, and is 3569 * not configured in the passthrough mode. 3570 */ 3571 if (no_iommu || iommu_default_passthrough()) { 3572 pr_err("SNP: IOMMU is disabled or configured in passthrough mode, SNP cannot be supported"); 3573 return -EINVAL; 3574 } 3575 3576 /* 3577 * Prevent enabling SNP after IOMMU_ENABLED state because this process 3578 * affect how IOMMU driver sets up data structures and configures 3579 * IOMMU hardware. 3580 */ 3581 if (init_state > IOMMU_ENABLED) { 3582 pr_err("SNP: Too late to enable SNP for IOMMU.\n"); 3583 return -EINVAL; 3584 } 3585 3586 amd_iommu_snp_en = check_feature_on_all_iommus(FEATURE_SNP); 3587 if (!amd_iommu_snp_en) 3588 return -EINVAL; 3589 3590 pr_info("SNP enabled\n"); 3591 3592 /* Enforce IOMMU v1 pagetable when SNP is enabled. */ 3593 if (amd_iommu_pgtable != AMD_IOMMU_V1) { 3594 pr_warn("Force to using AMD IOMMU v1 page table due to SNP\n"); 3595 amd_iommu_pgtable = AMD_IOMMU_V1; 3596 } 3597 3598 return 0; 3599} 3600#endif |
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