qp.c (70d40b366d2f7c2facaa3bc20f26e562e91ce94d) qp.c (e1f24a79f424ddb03828de7c0152668c9a30146e)
1/*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:

--- 2785 unchanged lines hidden (view full) ---

2794 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2795 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2796
2797 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2798 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
2799 qp->port) - 1;
2800 mibport = &dev->port[port_num];
2801 context->qp_counter_set_usr_page |=
1/*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:

--- 2785 unchanged lines hidden (view full) ---

2794 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2795 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2796
2797 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2798 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
2799 qp->port) - 1;
2800 mibport = &dev->port[port_num];
2801 context->qp_counter_set_usr_page |=
2802 cpu_to_be32((u32)(mibport->q_cnts.set_id) << 24);
2802 cpu_to_be32((u32)(mibport->cnts.set_id) << 24);
2803 }
2804
2805 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2806 context->sq_crq_size |= cpu_to_be16(1 << 4);
2807
2808 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
2809 context->deth_sqpn = cpu_to_be32(1);
2810

--- 11 unchanged lines hidden (view full) ---

2822 optpar = ib_mask_to_mlx5_opt(attr_mask);
2823 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
2824
2825 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
2826 struct mlx5_modify_raw_qp_param raw_qp_param = {};
2827
2828 raw_qp_param.operation = op;
2829 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2803 }
2804
2805 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2806 context->sq_crq_size |= cpu_to_be16(1 << 4);
2807
2808 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
2809 context->deth_sqpn = cpu_to_be32(1);
2810

--- 11 unchanged lines hidden (view full) ---

2822 optpar = ib_mask_to_mlx5_opt(attr_mask);
2823 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
2824
2825 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
2826 struct mlx5_modify_raw_qp_param raw_qp_param = {};
2827
2828 raw_qp_param.operation = op;
2829 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2830 raw_qp_param.rq_q_ctr_id = mibport->q_cnts.set_id;
2830 raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id;
2831 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
2832 }
2833
2834 if (attr_mask & IB_QP_RATE_LIMIT) {
2835 raw_qp_param.rate_limit = attr->rate_limit;
2836 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
2837 }
2838

--- 2121 unchanged lines hidden (view full) ---

4960 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
4961 }
4962 }
4963
4964 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
4965 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
4966 MLX5_SET64(modify_rq_in, in, modify_bitmask,
4967 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
2831 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
2832 }
2833
2834 if (attr_mask & IB_QP_RATE_LIMIT) {
2835 raw_qp_param.rate_limit = attr->rate_limit;
2836 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
2837 }
2838

--- 2121 unchanged lines hidden (view full) ---

4960 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
4961 }
4962 }
4963
4964 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
4965 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
4966 MLX5_SET64(modify_rq_in, in, modify_bitmask,
4967 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
4968 MLX5_SET(rqc, rqc, counter_set_id, dev->port->q_cnts.set_id);
4968 MLX5_SET(rqc, rqc, counter_set_id,
4969 dev->port->cnts.set_id);
4969 } else
4970 pr_info_once("%s: Receive WQ counters are not supported on current FW\n",
4971 dev->ib_dev.name);
4972 }
4973
4974 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
4975 if (!err)
4976 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
4977
4978out:
4979 kvfree(in);
4980 return err;
4981}
4970 } else
4971 pr_info_once("%s: Receive WQ counters are not supported on current FW\n",
4972 dev->ib_dev.name);
4973 }
4974
4975 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
4976 if (!err)
4977 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
4978
4979out:
4980 kvfree(in);
4981 return err;
4982}