main.c (5518b69b76680a4f2df96b1deca260059db0c2de) main.c (8e959601996dc645f4ed7004482a1667c27deb39)
1/*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:

--- 46 unchanged lines hidden (view full) ---

55#include <linux/in.h>
56#include <linux/etherdevice.h>
57#include <linux/mlx5/fs.h>
58#include <linux/mlx5/vport.h>
59#include "mlx5_ib.h"
60#include "cmd.h"
61
62#define DRIVER_NAME "mlx5_ib"
1/*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:

--- 46 unchanged lines hidden (view full) ---

55#include <linux/in.h>
56#include <linux/etherdevice.h>
57#include <linux/mlx5/fs.h>
58#include <linux/mlx5/vport.h>
59#include "mlx5_ib.h"
60#include "cmd.h"
61
62#define DRIVER_NAME "mlx5_ib"
63#define DRIVER_VERSION "5.0-0"
63#define DRIVER_VERSION "2.2-1"
64#define DRIVER_RELDATE "Feb 2014"
64
65MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
66MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
67MODULE_LICENSE("Dual BSD/GPL");
68MODULE_VERSION(DRIVER_VERSION);
69
70static char mlx5_version[] =
71 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
65
66MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
67MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
68MODULE_LICENSE("Dual BSD/GPL");
69MODULE_VERSION(DRIVER_VERSION);
70
71static char mlx5_version[] =
72 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
72 DRIVER_VERSION "\n";
73 DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
73
74enum {
75 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
76};
77
78static enum rdma_link_layer
79mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
80{

--- 137 unchanged lines hidden (view full) ---

218 break;
219 default:
220 return -EINVAL;
221 }
222
223 return 0;
224}
225
74
75enum {
76 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
77};
78
79static enum rdma_link_layer
80mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
81{

--- 137 unchanged lines hidden (view full) ---

219 break;
220 default:
221 return -EINVAL;
222 }
223
224 return 0;
225}
226
226static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
227 struct ib_port_attr *props)
227static void mlx5_query_port_roce(struct ib_device *device, u8 port_num,
228 struct ib_port_attr *props)
228{
229 struct mlx5_ib_dev *dev = to_mdev(device);
230 struct mlx5_core_dev *mdev = dev->mdev;
231 struct net_device *ndev, *upper;
232 enum ib_mtu ndev_ib_mtu;
233 u16 qkey_viol_cntr;
234 u32 eth_prot_oper;
229{
230 struct mlx5_ib_dev *dev = to_mdev(device);
231 struct mlx5_core_dev *mdev = dev->mdev;
232 struct net_device *ndev, *upper;
233 enum ib_mtu ndev_ib_mtu;
234 u16 qkey_viol_cntr;
235 u32 eth_prot_oper;
235 int err;
236
237 /* Possible bad flows are checked before filling out props so in case
238 * of an error it will still be zeroed out.
239 */
236
237 /* Possible bad flows are checked before filling out props so in case
238 * of an error it will still be zeroed out.
239 */
240 err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper, port_num);
241 if (err)
242 return err;
240 if (mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper, port_num))
241 return;
243
244 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
245 &props->active_width);
246
247 props->port_cap_flags |= IB_PORT_CM_SUP;
248 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
249
250 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,

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255 props->state = IB_PORT_DOWN;
256 props->phys_state = 3;
257
258 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
259 props->qkey_viol_cntr = qkey_viol_cntr;
260
261 ndev = mlx5_ib_get_netdev(device, port_num);
262 if (!ndev)
242
243 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
244 &props->active_width);
245
246 props->port_cap_flags |= IB_PORT_CM_SUP;
247 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
248
249 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,

--- 4 unchanged lines hidden (view full) ---

254 props->state = IB_PORT_DOWN;
255 props->phys_state = 3;
256
257 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
258 props->qkey_viol_cntr = qkey_viol_cntr;
259
260 ndev = mlx5_ib_get_netdev(device, port_num);
261 if (!ndev)
263 return 0;
262 return;
264
265 if (mlx5_lag_is_active(dev->mdev)) {
266 rcu_read_lock();
267 upper = netdev_master_upper_dev_get_rcu(ndev);
268 if (upper) {
269 dev_put(ndev);
270 ndev = upper;
271 dev_hold(ndev);

--- 6 unchanged lines hidden (view full) ---

278 props->phys_state = 5;
279 }
280
281 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
282
283 dev_put(ndev);
284
285 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
263
264 if (mlx5_lag_is_active(dev->mdev)) {
265 rcu_read_lock();
266 upper = netdev_master_upper_dev_get_rcu(ndev);
267 if (upper) {
268 dev_put(ndev);
269 ndev = upper;
270 dev_hold(ndev);

--- 6 unchanged lines hidden (view full) ---

277 props->phys_state = 5;
278 }
279
280 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
281
282 dev_put(ndev);
283
284 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
286 return 0;
287}
288
285}
286
289static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
290 unsigned int index, const union ib_gid *gid,
291 const struct ib_gid_attr *attr)
287static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
288 const struct ib_gid_attr *attr,
289 void *mlx5_addr)
292{
290{
293 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
294 u8 roce_version = 0;
295 u8 roce_l3_type = 0;
296 bool vlan = false;
297 u8 mac[ETH_ALEN];
298 u16 vlan_id = 0;
291#define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
292 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
293 source_l3_address);
294 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
295 source_mac_47_32);
299
296
300 if (gid) {
301 gid_type = attr->gid_type;
302 ether_addr_copy(mac, attr->ndev->dev_addr);
297 if (!gid)
298 return;
303
299
304 if (is_vlan_dev(attr->ndev)) {
305 vlan = true;
306 vlan_id = vlan_dev_vlan_id(attr->ndev);
307 }
300 ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr);
301
302 if (is_vlan_dev(attr->ndev)) {
303 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
304 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
308 }
309
305 }
306
310 switch (gid_type) {
307 switch (attr->gid_type) {
311 case IB_GID_TYPE_IB:
308 case IB_GID_TYPE_IB:
312 roce_version = MLX5_ROCE_VERSION_1;
309 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
313 break;
314 case IB_GID_TYPE_ROCE_UDP_ENCAP:
310 break;
311 case IB_GID_TYPE_ROCE_UDP_ENCAP:
315 roce_version = MLX5_ROCE_VERSION_2;
316 if (ipv6_addr_v4mapped((void *)gid))
317 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
318 else
319 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
312 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
320 break;
321
322 default:
313 break;
314
315 default:
323 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
316 WARN_ON(true);
324 }
325
317 }
318
326 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
327 roce_l3_type, gid->raw, mac, vlan,
328 vlan_id);
319 if (attr->gid_type != IB_GID_TYPE_IB) {
320 if (ipv6_addr_v4mapped((void *)gid))
321 MLX5_SET_RA(mlx5_addr, roce_l3_type,
322 MLX5_ROCE_L3_TYPE_IPV4);
323 else
324 MLX5_SET_RA(mlx5_addr, roce_l3_type,
325 MLX5_ROCE_L3_TYPE_IPV6);
326 }
327
328 if ((attr->gid_type == IB_GID_TYPE_IB) ||
329 !ipv6_addr_v4mapped((void *)gid))
330 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
331 else
332 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
329}
330
333}
334
335static int set_roce_addr(struct ib_device *device, u8 port_num,
336 unsigned int index,
337 const union ib_gid *gid,
338 const struct ib_gid_attr *attr)
339{
340 struct mlx5_ib_dev *dev = to_mdev(device);
341 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0};
342 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0};
343 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
344 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
345
346 if (ll != IB_LINK_LAYER_ETHERNET)
347 return -EINVAL;
348
349 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
350
351 MLX5_SET(set_roce_address_in, in, roce_address_index, index);
352 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
353 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
354}
355
331static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
332 unsigned int index, const union ib_gid *gid,
333 const struct ib_gid_attr *attr,
334 __always_unused void **context)
335{
356static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
357 unsigned int index, const union ib_gid *gid,
358 const struct ib_gid_attr *attr,
359 __always_unused void **context)
360{
336 return set_roce_addr(to_mdev(device), port_num, index, gid, attr);
361 return set_roce_addr(device, port_num, index, gid, attr);
337}
338
339static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
340 unsigned int index, __always_unused void **context)
341{
362}
363
364static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
365 unsigned int index, __always_unused void **context)
366{
342 return set_roce_addr(to_mdev(device), port_num, index, NULL, NULL);
367 return set_roce_addr(device, port_num, index, NULL, NULL);
343}
344
345__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
346 int index)
347{
348 struct ib_gid_attr attr;
349 union ib_gid gid;
350

--- 59 unchanged lines hidden (view full) ---

410
411static void get_atomic_caps(struct mlx5_ib_dev *dev,
412 struct ib_device_attr *props)
413{
414 u8 tmp;
415 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
416 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
417 u8 atomic_req_8B_endianness_mode =
368}
369
370__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
371 int index)
372{
373 struct ib_gid_attr attr;
374 union ib_gid gid;
375

--- 59 unchanged lines hidden (view full) ---

435
436static void get_atomic_caps(struct mlx5_ib_dev *dev,
437 struct ib_device_attr *props)
438{
439 u8 tmp;
440 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
441 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
442 u8 atomic_req_8B_endianness_mode =
418 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
443 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
419
420 /* Check if HW supports 8 bytes standard atomic operations and capable
421 * of host endianness respond
422 */
423 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
424 if (((atomic_operations & tmp) == tmp) &&
425 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
426 (atomic_req_8B_endianness_mode)) {

--- 522 unchanged lines hidden (view full) ---

949out:
950 kfree(rep);
951 return err;
952}
953
954int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
955 struct ib_port_attr *props)
956{
444
445 /* Check if HW supports 8 bytes standard atomic operations and capable
446 * of host endianness respond
447 */
448 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
449 if (((atomic_operations & tmp) == tmp) &&
450 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
451 (atomic_req_8B_endianness_mode)) {

--- 522 unchanged lines hidden (view full) ---

974out:
975 kfree(rep);
976 return err;
977}
978
979int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
980 struct ib_port_attr *props)
981{
957 unsigned int count;
958 int ret;
959
960 switch (mlx5_get_vport_access_method(ibdev)) {
961 case MLX5_VPORT_ACCESS_METHOD_MAD:
982 switch (mlx5_get_vport_access_method(ibdev)) {
983 case MLX5_VPORT_ACCESS_METHOD_MAD:
962 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
963 break;
984 return mlx5_query_mad_ifc_port(ibdev, port, props);
964
965 case MLX5_VPORT_ACCESS_METHOD_HCA:
985
986 case MLX5_VPORT_ACCESS_METHOD_HCA:
966 ret = mlx5_query_hca_port(ibdev, port, props);
967 break;
987 return mlx5_query_hca_port(ibdev, port, props);
968
969 case MLX5_VPORT_ACCESS_METHOD_NIC:
988
989 case MLX5_VPORT_ACCESS_METHOD_NIC:
970 ret = mlx5_query_port_roce(ibdev, port, props);
971 break;
990 mlx5_query_port_roce(ibdev, port, props);
991 return 0;
972
973 default:
992
993 default:
974 ret = -EINVAL;
994 return -EINVAL;
975 }
995 }
976
977 if (!ret && props) {
978 count = mlx5_core_reserved_gids_count(to_mdev(ibdev)->mdev);
979 props->gid_tbl_len -= count;
980 }
981 return ret;
982}
983
984static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
985 union ib_gid *gid)
986{
987 struct mlx5_ib_dev *dev = to_mdev(ibdev);
988 struct mlx5_core_dev *mdev = dev->mdev;
989

--- 1254 unchanged lines hidden (view full) ---

2244 u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
2245 bool is_drop = false;
2246 int err = 0;
2247 int dest_num = 1;
2248
2249 if (!is_valid_attr(dev->mdev, flow_attr))
2250 return ERR_PTR(-EINVAL);
2251
996}
997
998static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
999 union ib_gid *gid)
1000{
1001 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1002 struct mlx5_core_dev *mdev = dev->mdev;
1003

--- 1254 unchanged lines hidden (view full) ---

2258 u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
2259 bool is_drop = false;
2260 int err = 0;
2261 int dest_num = 1;
2262
2263 if (!is_valid_attr(dev->mdev, flow_attr))
2264 return ERR_PTR(-EINVAL);
2265
2252 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
2266 spec = mlx5_vzalloc(sizeof(*spec));
2253 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
2254 if (!handler || !spec) {
2255 err = -ENOMEM;
2256 goto free;
2257 }
2258
2259 INIT_LIST_HEAD(&handler->list);
2260

--- 1188 unchanged lines hidden (view full) ---

3449 struct mlx5_ib_port *port,
3450 struct rdma_hw_stats *stats)
3451{
3452 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
3453 void *out;
3454 __be32 val;
3455 int ret, i;
3456
2267 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
2268 if (!handler || !spec) {
2269 err = -ENOMEM;
2270 goto free;
2271 }
2272
2273 INIT_LIST_HEAD(&handler->list);
2274

--- 1188 unchanged lines hidden (view full) ---

3463 struct mlx5_ib_port *port,
3464 struct rdma_hw_stats *stats)
3465{
3466 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
3467 void *out;
3468 __be32 val;
3469 int ret, i;
3470
3457 out = kvzalloc(outlen, GFP_KERNEL);
3471 out = mlx5_vzalloc(outlen);
3458 if (!out)
3459 return -ENOMEM;
3460
3461 ret = mlx5_core_query_q_counter(dev->mdev,
3462 port->cnts.set_id, 0,
3463 out, outlen);
3464 if (ret)
3465 goto free;

--- 12 unchanged lines hidden (view full) ---

3478 struct mlx5_ib_port *port,
3479 struct rdma_hw_stats *stats)
3480{
3481 int outlen = MLX5_ST_SZ_BYTES(query_cong_statistics_out);
3482 void *out;
3483 int ret, i;
3484 int offset = port->cnts.num_q_counters;
3485
3472 if (!out)
3473 return -ENOMEM;
3474
3475 ret = mlx5_core_query_q_counter(dev->mdev,
3476 port->cnts.set_id, 0,
3477 out, outlen);
3478 if (ret)
3479 goto free;

--- 12 unchanged lines hidden (view full) ---

3492 struct mlx5_ib_port *port,
3493 struct rdma_hw_stats *stats)
3494{
3495 int outlen = MLX5_ST_SZ_BYTES(query_cong_statistics_out);
3496 void *out;
3497 int ret, i;
3498 int offset = port->cnts.num_q_counters;
3499
3486 out = kvzalloc(outlen, GFP_KERNEL);
3500 out = mlx5_vzalloc(outlen);
3487 if (!out)
3488 return -ENOMEM;
3489
3490 ret = mlx5_cmd_query_cong_counter(dev->mdev, false, out, outlen);
3491 if (ret)
3492 goto free;
3493
3494 for (i = 0; i < port->cnts.num_cong_counters; i++) {

--- 28 unchanged lines hidden (view full) ---

3523 if (ret)
3524 return ret;
3525 num_counters += port->cnts.num_cong_counters;
3526 }
3527
3528 return num_counters;
3529}
3530
3501 if (!out)
3502 return -ENOMEM;
3503
3504 ret = mlx5_cmd_query_cong_counter(dev->mdev, false, out, outlen);
3505 if (ret)
3506 goto free;
3507
3508 for (i = 0; i < port->cnts.num_cong_counters; i++) {

--- 28 unchanged lines hidden (view full) ---

3537 if (ret)
3538 return ret;
3539 num_counters += port->cnts.num_cong_counters;
3540 }
3541
3542 return num_counters;
3543}
3544
3545static void mlx5_ib_free_rdma_netdev(struct net_device *netdev)
3546{
3547 return mlx5_rdma_netdev_free(netdev);
3548}
3549
3531static struct net_device*
3532mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
3533 u8 port_num,
3534 enum rdma_netdev_t type,
3535 const char *name,
3536 unsigned char name_assign_type,
3537 void (*setup)(struct net_device *))
3538{
3550static struct net_device*
3551mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
3552 u8 port_num,
3553 enum rdma_netdev_t type,
3554 const char *name,
3555 unsigned char name_assign_type,
3556 void (*setup)(struct net_device *))
3557{
3558 struct net_device *netdev;
3559 struct rdma_netdev *rn;
3560
3539 if (type != RDMA_NETDEV_IPOIB)
3540 return ERR_PTR(-EOPNOTSUPP);
3541
3561 if (type != RDMA_NETDEV_IPOIB)
3562 return ERR_PTR(-EOPNOTSUPP);
3563
3542 return mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
3543 name, setup);
3564 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
3565 name, setup);
3566 if (likely(!IS_ERR_OR_NULL(netdev))) {
3567 rn = netdev_priv(netdev);
3568 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev;
3569 }
3570 return netdev;
3544}
3545
3571}
3572
3546static void mlx5_ib_free_rdma_netdev(struct net_device *netdev)
3547{
3548 return mlx5_rdma_netdev_free(netdev);
3549}
3550
3551static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
3552{
3553 struct mlx5_ib_dev *dev;
3554 enum rdma_link_layer ll;
3555 int port_type_cap;
3556 const char *name;
3557 int err;
3558 int i;

--- 114 unchanged lines hidden (view full) ---

3673 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
3674 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
3675 dev->ib_dev.process_mad = mlx5_ib_process_mad;
3676 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
3677 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
3678 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
3679 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
3680 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
3573static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
3574{
3575 struct mlx5_ib_dev *dev;
3576 enum rdma_link_layer ll;
3577 int port_type_cap;
3578 const char *name;
3579 int err;
3580 int i;

--- 114 unchanged lines hidden (view full) ---

3695 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
3696 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
3697 dev->ib_dev.process_mad = mlx5_ib_process_mad;
3698 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
3699 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
3700 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
3701 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
3702 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
3681 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads)) {
3703 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
3682 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev;
3704 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev;
3683 dev->ib_dev.free_rdma_netdev = mlx5_ib_free_rdma_netdev;
3684 }
3705
3685 if (mlx5_core_is_pf(mdev)) {
3686 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
3687 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
3688 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
3689 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
3690 }
3691
3692 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;

--- 193 unchanged lines hidden --- 		3706 if (mlx5_core_is_pf(mdev)) {
3707 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
3708 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
3709 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
3710 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
3711 }
3712
3713 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;

--- 193 unchanged lines hidden ---