main.c (446279168e030fd0ed68e2bba336bef8bb3da352) main.c (13ad1125b941a5f257d9d3ae70485773abd34792)
1// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2/*
3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved.
4 * Copyright (c) 2020, Intel Corporation. All rights reserved.
5 */
6
7#include <linux/debugfs.h>
8#include <linux/highmem.h>

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1821 resp->comp_mask |=
1822 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS;
1823
1824 resp->num_dyn_bfregs = bfregi->num_dyn_bfregs;
1825
1826 if (MLX5_CAP_GEN(dev->mdev, drain_sigerr))
1827 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS;
1828
1// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2/*
3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved.
4 * Copyright (c) 2020, Intel Corporation. All rights reserved.
5 */
6
7#include <linux/debugfs.h>
8#include <linux/highmem.h>

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1821 resp->comp_mask |=
1822 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS;
1823
1824 resp->num_dyn_bfregs = bfregi->num_dyn_bfregs;
1825
1826 if (MLX5_CAP_GEN(dev->mdev, drain_sigerr))
1827 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS;
1828
1829 resp->comp_mask |=
1830 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_MKEY_UPDATE_TAG;
1831
1829 return 0;
1830}
1831
1832static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx,
1833 struct ib_udata *udata)
1834{
1835 struct ib_device *ibdev = uctx->device;
1836 struct mlx5_ib_dev *dev = to_mdev(ibdev);

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3997 name = "mlx5_bond_%d";
3998 return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev);
3999}
4000
4001static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
4002{
4003 int err;
4004
1832 return 0;
1833}
1834
1835static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx,
1836 struct ib_udata *udata)
1837{
1838 struct ib_device *ibdev = uctx->device;
1839 struct mlx5_ib_dev *dev = to_mdev(ibdev);

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4000 name = "mlx5_bond_%d";
4001 return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev);
4002}
4003
4004static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
4005{
4006 int err;
4007
4005 err = mlx5_mr_cache_cleanup(dev);
4008 err = mlx5_mkey_cache_cleanup(dev);
4006 if (err)
4007 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4008
4009 mlx5r_umr_resource_cleanup(dev);
4010}
4011
4012static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
4013{
4014 ib_unregister_device(&dev->ib_dev);
4015}
4016
4017static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
4018{
4019 int ret;
4020
4021 ret = mlx5r_umr_resource_init(dev);
4022 if (ret)
4023 return ret;
4024
4009 if (err)
4010 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4011
4012 mlx5r_umr_resource_cleanup(dev);
4013}
4014
4015static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
4016{
4017 ib_unregister_device(&dev->ib_dev);
4018}
4019
4020static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
4021{
4022 int ret;
4023
4024 ret = mlx5r_umr_resource_init(dev);
4025 if (ret)
4026 return ret;
4027
4025 ret = mlx5_mr_cache_init(dev);
4028 ret = mlx5_mkey_cache_init(dev);
4026 if (ret) {
4027 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4028 mlx5r_umr_resource_cleanup(dev);
4029 }
4030 return ret;
4031}
4032
4033static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)

--- 406 unchanged lines hidden --- 		4029 if (ret) {
4030 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4031 mlx5r_umr_resource_cleanup(dev);
4032 }
4033 return ret;
4034}
4035
4036static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)

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