cmd.c (cbecf716ca618fd44feda6bd9a64a8179d031fc5) cmd.c (831df88381f73bca0f5624b69ab985cac3d036bc)
1// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2/*
3 * Copyright (c) 2017-2020, Mellanox Technologies inc. All rights reserved.
4 */
5
6#include "cmd.h"
7
8int mlx5_cmd_dump_fill_mkey(struct mlx5_core_dev *dev, u32 *mkey)

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42
43 MLX5_SET(query_cong_params_in, in, opcode,
44 MLX5_CMD_OP_QUERY_CONG_PARAMS);
45 MLX5_SET(query_cong_params_in, in, cong_protocol, cong_point);
46
47 return mlx5_cmd_exec_inout(dev, query_cong_params, in, out);
48}
49
1// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2/*
3 * Copyright (c) 2017-2020, Mellanox Technologies inc. All rights reserved.
4 */
5
6#include "cmd.h"
7
8int mlx5_cmd_dump_fill_mkey(struct mlx5_core_dev *dev, u32 *mkey)

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42
43 MLX5_SET(query_cong_params_in, in, opcode,
44 MLX5_CMD_OP_QUERY_CONG_PARAMS);
45 MLX5_SET(query_cong_params_in, in, cong_protocol, cong_point);
46
47 return mlx5_cmd_exec_inout(dev, query_cong_params, in, out);
48}
49
50int mlx5_cmd_alloc_memic(struct mlx5_dm *dm, phys_addr_t *addr,
51 u64 length, u32 alignment)
52{
53 struct mlx5_core_dev *dev = dm->dev;
54 u64 num_memic_hw_pages = MLX5_CAP_DEV_MEM(dev, memic_bar_size)
55 >> PAGE_SHIFT;
56 u64 hw_start_addr = MLX5_CAP64_DEV_MEM(dev, memic_bar_start_addr);
57 u32 max_alignment = MLX5_CAP_DEV_MEM(dev, log_max_memic_addr_alignment);
58 u32 num_pages = DIV_ROUND_UP(length, PAGE_SIZE);
59 u32 out[MLX5_ST_SZ_DW(alloc_memic_out)] = {};
60 u32 in[MLX5_ST_SZ_DW(alloc_memic_in)] = {};
61 u32 mlx5_alignment;
62 u64 page_idx = 0;
63 int ret = 0;
64
65 if (!length || (length & MLX5_MEMIC_ALLOC_SIZE_MASK))
66 return -EINVAL;
67
68 /* mlx5 device sets alignment as 64*2^driver_value
69 * so normalizing is needed.
70 */
71 mlx5_alignment = (alignment < MLX5_MEMIC_BASE_ALIGN) ? 0 :
72 alignment - MLX5_MEMIC_BASE_ALIGN;
73 if (mlx5_alignment > max_alignment)
74 return -EINVAL;
75
76 MLX5_SET(alloc_memic_in, in, opcode, MLX5_CMD_OP_ALLOC_MEMIC);
77 MLX5_SET(alloc_memic_in, in, range_size, num_pages * PAGE_SIZE);
78 MLX5_SET(alloc_memic_in, in, memic_size, length);
79 MLX5_SET(alloc_memic_in, in, log_memic_addr_alignment,
80 mlx5_alignment);
81
82 while (page_idx < num_memic_hw_pages) {
83 spin_lock(&dm->lock);
84 page_idx = bitmap_find_next_zero_area(dm->memic_alloc_pages,
85 num_memic_hw_pages,
86 page_idx,
87 num_pages, 0);
88
89 if (page_idx < num_memic_hw_pages)
90 bitmap_set(dm->memic_alloc_pages,
91 page_idx, num_pages);
92
93 spin_unlock(&dm->lock);
94
95 if (page_idx >= num_memic_hw_pages)
96 break;
97
98 MLX5_SET64(alloc_memic_in, in, range_start_addr,
99 hw_start_addr + (page_idx * PAGE_SIZE));
100
101 ret = mlx5_cmd_exec_inout(dev, alloc_memic, in, out);
102 if (ret) {
103 spin_lock(&dm->lock);
104 bitmap_clear(dm->memic_alloc_pages,
105 page_idx, num_pages);
106 spin_unlock(&dm->lock);
107
108 if (ret == -EAGAIN) {
109 page_idx++;
110 continue;
111 }
112
113 return ret;
114 }
115
116 *addr = dev->bar_addr +
117 MLX5_GET64(alloc_memic_out, out, memic_start_addr);
118
119 return 0;
120 }
121
122 return -ENOMEM;
123}
124
125void mlx5_cmd_dealloc_memic(struct mlx5_dm *dm, phys_addr_t addr, u64 length)
126{
127 struct mlx5_core_dev *dev = dm->dev;
128 u64 hw_start_addr = MLX5_CAP64_DEV_MEM(dev, memic_bar_start_addr);
129 u32 num_pages = DIV_ROUND_UP(length, PAGE_SIZE);
130 u32 in[MLX5_ST_SZ_DW(dealloc_memic_in)] = {};
131 u64 start_page_idx;
132 int err;
133
134 addr -= dev->bar_addr;
135 start_page_idx = (addr - hw_start_addr) >> PAGE_SHIFT;
136
137 MLX5_SET(dealloc_memic_in, in, opcode, MLX5_CMD_OP_DEALLOC_MEMIC);
138 MLX5_SET64(dealloc_memic_in, in, memic_start_addr, addr);
139 MLX5_SET(dealloc_memic_in, in, memic_size, length);
140
141 err = mlx5_cmd_exec_in(dev, dealloc_memic, in);
142 if (err)
143 return;
144
145 spin_lock(&dm->lock);
146 bitmap_clear(dm->memic_alloc_pages,
147 start_page_idx, num_pages);
148 spin_unlock(&dm->lock);
149}
150
151void mlx5_cmd_destroy_tir(struct mlx5_core_dev *dev, u32 tirn, u16 uid)
152{
153 u32 in[MLX5_ST_SZ_DW(destroy_tir_in)] = {};
154
155 MLX5_SET(destroy_tir_in, in, opcode, MLX5_CMD_OP_DESTROY_TIR);
156 MLX5_SET(destroy_tir_in, in, tirn, tirn);
157 MLX5_SET(destroy_tir_in, in, uid, uid);
158 mlx5_cmd_exec_in(dev, destroy_tir, in);

--- 151 unchanged lines hidden --- 		50void mlx5_cmd_destroy_tir(struct mlx5_core_dev *dev, u32 tirn, u16 uid)
51{
52 u32 in[MLX5_ST_SZ_DW(destroy_tir_in)] = {};
53
54 MLX5_SET(destroy_tir_in, in, opcode, MLX5_CMD_OP_DESTROY_TIR);
55 MLX5_SET(destroy_tir_in, in, tirn, tirn);
56 MLX5_SET(destroy_tir_in, in, uid, uid);
57 mlx5_cmd_exec_in(dev, destroy_tir, in);

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