hw.c (651a88798412e216f337d70181127e847f00a4b7) hw.c (81091d7696ae71627ff80bbf2c6b0986d2c1cce3)
1// SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
2/* Copyright (c) 2015 - 2021 Intel Corporation */
3#include "main.h"
4
5static struct irdma_rsrc_limits rsrc_limits_table[] = {
6 [0] = {
7 .qplimit = SZ_128,
8 },

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56 * irdma_iwarp_ce_handler - handle iwarp completions
57 * @iwcq: iwarp cq receiving event
58 */
59static void irdma_iwarp_ce_handler(struct irdma_sc_cq *iwcq)
60{
61 struct irdma_cq *cq = iwcq->back_cq;
62
63 if (!cq->user_mode)
1// SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
2/* Copyright (c) 2015 - 2021 Intel Corporation */
3#include "main.h"
4
5static struct irdma_rsrc_limits rsrc_limits_table[] = {
6 [0] = {
7 .qplimit = SZ_128,
8 },

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56 * irdma_iwarp_ce_handler - handle iwarp completions
57 * @iwcq: iwarp cq receiving event
58 */
59static void irdma_iwarp_ce_handler(struct irdma_sc_cq *iwcq)
60{
61 struct irdma_cq *cq = iwcq->back_cq;
62
63 if (!cq->user_mode)
64 cq->armed = false;
64 atomic_set(&cq->armed, 0);
65 if (cq->ibcq.comp_handler)
66 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
67}
68
69/**
70 * irdma_puda_ce_handler - handle puda completion events
71 * @rf: RDMA PCI function
72 * @cq: puda completion q for event

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1822 irdma_destroy_pble_prm(rf->pble_rsrc);
1823 irdma_del_ceqs(rf);
1824 break;
1825 }
1826 iwdev->init_state = AEQ_CREATED;
1827 rf->rsrc_created = true;
1828 }
1829
65 if (cq->ibcq.comp_handler)
66 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
67}
68
69/**
70 * irdma_puda_ce_handler - handle puda completion events
71 * @rf: RDMA PCI function
72 * @cq: puda completion q for event

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1822 irdma_destroy_pble_prm(rf->pble_rsrc);
1823 irdma_del_ceqs(rf);
1824 break;
1825 }
1826 iwdev->init_state = AEQ_CREATED;
1827 rf->rsrc_created = true;
1828 }
1829
1830 iwdev->device_cap_flags = IB_DEVICE_LOCAL_DMA_LKEY |
1831 IB_DEVICE_MEM_WINDOW |
1832 IB_DEVICE_MEM_MGT_EXTENSIONS;
1833
1834 if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1)
1835 irdma_alloc_set_mac(iwdev);
1836 irdma_add_ip(iwdev);
1837 iwdev->init_state = IP_ADDR_REGISTERED;
1838
1839 /* handles asynch cleanup tasks - disconnect CM , free qp,
1840 * free cq bufs
1841 */

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2688
2689 if (!(flush_mask & IRDMA_FLUSH_SQ) && !(flush_mask & IRDMA_FLUSH_RQ))
2690 return;
2691
2692 /* Set flush info fields*/
2693 info.sq = flush_mask & IRDMA_FLUSH_SQ;
2694 info.rq = flush_mask & IRDMA_FLUSH_RQ;
2695
1830 if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1)
1831 irdma_alloc_set_mac(iwdev);
1832 irdma_add_ip(iwdev);
1833 iwdev->init_state = IP_ADDR_REGISTERED;
1834
1835 /* handles asynch cleanup tasks - disconnect CM , free qp,
1836 * free cq bufs
1837 */

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2684
2685 if (!(flush_mask & IRDMA_FLUSH_SQ) && !(flush_mask & IRDMA_FLUSH_RQ))
2686 return;
2687
2688 /* Set flush info fields*/
2689 info.sq = flush_mask & IRDMA_FLUSH_SQ;
2690 info.rq = flush_mask & IRDMA_FLUSH_RQ;
2691
2696 if (flush_mask & IRDMA_REFLUSH) {
2697 if (info.sq)
2698 iwqp->sc_qp.flush_sq = false;
2699 if (info.rq)
2700 iwqp->sc_qp.flush_rq = false;
2701 }
2702
2703 /* Generate userflush errors in CQE */
2704 info.sq_major_code = IRDMA_FLUSH_MAJOR_ERR;
2705 info.sq_minor_code = FLUSH_GENERAL_ERR;
2706 info.rq_major_code = IRDMA_FLUSH_MAJOR_ERR;
2707 info.rq_minor_code = FLUSH_GENERAL_ERR;
2708 info.userflushcode = true;
2692 /* Generate userflush errors in CQE */
2693 info.sq_major_code = IRDMA_FLUSH_MAJOR_ERR;
2694 info.sq_minor_code = FLUSH_GENERAL_ERR;
2695 info.rq_major_code = IRDMA_FLUSH_MAJOR_ERR;
2696 info.rq_minor_code = FLUSH_GENERAL_ERR;
2697 info.userflushcode = true;
2709 if (flush_code) {
2710 if (info.sq && iwqp->sc_qp.sq_flush_code)
2711 info.sq_minor_code = flush_code;
2712 if (info.rq && iwqp->sc_qp.rq_flush_code)
2713 info.rq_minor_code = flush_code;
2698
2699 if (flush_mask & IRDMA_REFLUSH) {
2700 if (info.sq)
2701 iwqp->sc_qp.flush_sq = false;
2702 if (info.rq)
2703 iwqp->sc_qp.flush_rq = false;
2704 } else {
2705 if (flush_code) {
2706 if (info.sq && iwqp->sc_qp.sq_flush_code)
2707 info.sq_minor_code = flush_code;
2708 if (info.rq && iwqp->sc_qp.rq_flush_code)
2709 info.rq_minor_code = flush_code;
2710 }
2711 if (!iwqp->user_mode)
2712 queue_delayed_work(iwqp->iwdev->cleanup_wq,
2713 &iwqp->dwork_flush,
2714 msecs_to_jiffies(IRDMA_FLUSH_DELAY_MS));
2714 }
2715
2716 /* Issue flush */
2717 (void)irdma_hw_flush_wqes(rf, &iwqp->sc_qp, &info,
2718 flush_mask & IRDMA_FLUSH_WAIT);
2719 iwqp->flush_issued = true;
2720}
2715 }
2716
2717 /* Issue flush */
2718 (void)irdma_hw_flush_wqes(rf, &iwqp->sc_qp, &info,
2719 flush_mask & IRDMA_FLUSH_WAIT);
2720 iwqp->flush_issued = true;
2721}