chip.c (0db9dec2762e02ee596bc2b9870414d5100d0baf) chip.c (60368186fd853899c1819bcefa47f85fe8d5e5ad)
1/*
2 * Copyright(c) 2015, 2016 Intel Corporation.
3 *
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
6 *
7 * GPL LICENSE SUMMARY
8 *

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11548 hfi1_cdbg(RCVCTRL, "ctxt %d op 0x%x", ctxt, op);
11549
11550 rcvctrl = read_kctxt_csr(dd, ctxt, RCV_CTXT_CTRL);
11551 /* if the context already enabled, don't do the extra steps */
11552 if ((op & HFI1_RCVCTRL_CTXT_ENB) &&
11553 !(rcvctrl & RCV_CTXT_CTRL_ENABLE_SMASK)) {
11554 /* reset the tail and hdr addresses, and sequence count */
11555 write_kctxt_csr(dd, ctxt, RCV_HDR_ADDR,
1/*
2 * Copyright(c) 2015, 2016 Intel Corporation.
3 *
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
6 *
7 * GPL LICENSE SUMMARY
8 *

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11548 hfi1_cdbg(RCVCTRL, "ctxt %d op 0x%x", ctxt, op);
11549
11550 rcvctrl = read_kctxt_csr(dd, ctxt, RCV_CTXT_CTRL);
11551 /* if the context already enabled, don't do the extra steps */
11552 if ((op & HFI1_RCVCTRL_CTXT_ENB) &&
11553 !(rcvctrl & RCV_CTXT_CTRL_ENABLE_SMASK)) {
11554 /* reset the tail and hdr addresses, and sequence count */
11555 write_kctxt_csr(dd, ctxt, RCV_HDR_ADDR,
11556 rcd->rcvhdrq_phys);
11556 rcd->rcvhdrq_dma);
11557 if (HFI1_CAP_KGET_MASK(rcd->flags, DMA_RTAIL))
11558 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
11557 if (HFI1_CAP_KGET_MASK(rcd->flags, DMA_RTAIL))
11558 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
11559 rcd->rcvhdrqtailaddr_phys);
11559 rcd->rcvhdrqtailaddr_dma);
11560 rcd->seq_cnt = 1;
11561
11562 /* reset the cached receive header queue head value */
11563 rcd->head = 0;
11564
11565 /*
11566 * Zero the receive header queue so we don't get false
11567 * positives when checking the sequence number. The

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11616 }
11617 if (op & HFI1_RCVCTRL_CTXT_DIS) {
11618 write_csr(dd, RCV_VL15, 0);
11619 /*
11620 * When receive context is being disabled turn on tail
11621 * update with a dummy tail address and then disable
11622 * receive context.
11623 */
11560 rcd->seq_cnt = 1;
11561
11562 /* reset the cached receive header queue head value */
11563 rcd->head = 0;
11564
11565 /*
11566 * Zero the receive header queue so we don't get false
11567 * positives when checking the sequence number. The

--- 48 unchanged lines hidden (view full) ---

11616 }
11617 if (op & HFI1_RCVCTRL_CTXT_DIS) {
11618 write_csr(dd, RCV_VL15, 0);
11619 /*
11620 * When receive context is being disabled turn on tail
11621 * update with a dummy tail address and then disable
11622 * receive context.
11623 */
11624 if (dd->rcvhdrtail_dummy_physaddr) {
11624 if (dd->rcvhdrtail_dummy_dma) {
11625 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
11625 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
11626 dd->rcvhdrtail_dummy_physaddr);
11626 dd->rcvhdrtail_dummy_dma);
11627 /* Enabling RcvCtxtCtrl.TailUpd is intentional. */
11628 rcvctrl |= RCV_CTXT_CTRL_TAIL_UPD_SMASK;
11629 }
11630
11631 rcvctrl &= ~RCV_CTXT_CTRL_ENABLE_SMASK;
11632 }
11633 if (op & HFI1_RCVCTRL_INTRAVAIL_ENB)
11634 rcvctrl |= RCV_CTXT_CTRL_INTR_AVAIL_SMASK;
11635 if (op & HFI1_RCVCTRL_INTRAVAIL_DIS)
11636 rcvctrl &= ~RCV_CTXT_CTRL_INTR_AVAIL_SMASK;
11627 /* Enabling RcvCtxtCtrl.TailUpd is intentional. */
11628 rcvctrl |= RCV_CTXT_CTRL_TAIL_UPD_SMASK;
11629 }
11630
11631 rcvctrl &= ~RCV_CTXT_CTRL_ENABLE_SMASK;
11632 }
11633 if (op & HFI1_RCVCTRL_INTRAVAIL_ENB)
11634 rcvctrl |= RCV_CTXT_CTRL_INTR_AVAIL_SMASK;
11635 if (op & HFI1_RCVCTRL_INTRAVAIL_DIS)
11636 rcvctrl &= ~RCV_CTXT_CTRL_INTR_AVAIL_SMASK;
11637 if (op & HFI1_RCVCTRL_TAILUPD_ENB && rcd->rcvhdrqtailaddr_phys)
11637 if (op & HFI1_RCVCTRL_TAILUPD_ENB && rcd->rcvhdrqtailaddr_dma)
11638 rcvctrl |= RCV_CTXT_CTRL_TAIL_UPD_SMASK;
11639 if (op & HFI1_RCVCTRL_TAILUPD_DIS) {
11640 /* See comment on RcvCtxtCtrl.TailUpd above */
11641 if (!(op & HFI1_RCVCTRL_CTXT_DIS))
11642 rcvctrl &= ~RCV_CTXT_CTRL_TAIL_UPD_SMASK;
11643 }
11644 if (op & HFI1_RCVCTRL_TIDFLOW_ENB)
11645 rcvctrl |= RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK;

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11701
11702 if (op & (HFI1_RCVCTRL_TAILUPD_DIS | HFI1_RCVCTRL_CTXT_DIS))
11703 /*
11704 * If the context has been disabled and the Tail Update has
11705 * been cleared, set the RCV_HDR_TAIL_ADDR CSR to dummy address
11706 * so it doesn't contain an address that is invalid.
11707 */
11708 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
11638 rcvctrl |= RCV_CTXT_CTRL_TAIL_UPD_SMASK;
11639 if (op & HFI1_RCVCTRL_TAILUPD_DIS) {
11640 /* See comment on RcvCtxtCtrl.TailUpd above */
11641 if (!(op & HFI1_RCVCTRL_CTXT_DIS))
11642 rcvctrl &= ~RCV_CTXT_CTRL_TAIL_UPD_SMASK;
11643 }
11644 if (op & HFI1_RCVCTRL_TIDFLOW_ENB)
11645 rcvctrl |= RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK;

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11701
11702 if (op & (HFI1_RCVCTRL_TAILUPD_DIS | HFI1_RCVCTRL_CTXT_DIS))
11703 /*
11704 * If the context has been disabled and the Tail Update has
11705 * been cleared, set the RCV_HDR_TAIL_ADDR CSR to dummy address
11706 * so it doesn't contain an address that is invalid.
11707 */
11708 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
11709 dd->rcvhdrtail_dummy_physaddr);
11709 dd->rcvhdrtail_dummy_dma);
11710}
11711
11712u32 hfi1_read_cntrs(struct hfi1_devdata *dd, char **namep, u64 **cntrp)
11713{
11714 int ret;
11715 u64 val = 0;
11716
11717 if (namep) {

--- 3163 unchanged lines hidden --- 		11710}
11711
11712u32 hfi1_read_cntrs(struct hfi1_devdata *dd, char **namep, u64 **cntrp)
11713{
11714 int ret;
11715 u64 val = 0;
11716
11717 if (namep) {

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