t4.h (301a36fa700f9add6e14f5a95c7573e01578343a) t4.h (49b53a93a64ab0aaec10851b004297a3ac885433)
1/*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:

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90union t4_wr {
91 struct fw_ri_res_wr res;
92 struct fw_ri_wr ri;
93 struct fw_ri_rdma_write_wr write;
94 struct fw_ri_send_wr send;
95 struct fw_ri_rdma_read_wr read;
96 struct fw_ri_bind_mw_wr bind;
97 struct fw_ri_fr_nsmr_wr fr;
1/*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:

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90union t4_wr {
91 struct fw_ri_res_wr res;
92 struct fw_ri_wr ri;
93 struct fw_ri_rdma_write_wr write;
94 struct fw_ri_send_wr send;
95 struct fw_ri_rdma_read_wr read;
96 struct fw_ri_bind_mw_wr bind;
97 struct fw_ri_fr_nsmr_wr fr;
98 struct fw_ri_fr_nsmr_tpte_wr fr_tpte;
98 struct fw_ri_inv_lstag_wr inv;
99 struct t4_status_page status;
100 __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_SQ_NUM_SLOTS];
101};
102
103union t4_recv_wr {
104 struct fw_ri_recv_wr recv;
105 struct t4_status_page status;

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165 __be32 header;
166 __be32 len;
167 union {
168 struct {
169 __be32 stag;
170 __be32 msn;
171 } rcqe;
172 struct {
99 struct fw_ri_inv_lstag_wr inv;
100 struct t4_status_page status;
101 __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_SQ_NUM_SLOTS];
102};
103
104union t4_recv_wr {
105 struct fw_ri_recv_wr recv;
106 struct t4_status_page status;

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166 __be32 header;
167 __be32 len;
168 union {
169 struct {
170 __be32 stag;
171 __be32 msn;
172 } rcqe;
173 struct {
173 u32 nada1;
174 u32 stag;
174 u16 nada2;
175 u16 cidx;
176 } scqe;
177 struct {
178 __be32 wrid_hi;
179 __be32 wrid_low;
180 } gen;
181 } u;

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227#define CQE_LEN(x) (be32_to_cpu((x)->len))
228
229/* used for RQ completion processing */
230#define CQE_WRID_STAG(x) (be32_to_cpu((x)->u.rcqe.stag))
231#define CQE_WRID_MSN(x) (be32_to_cpu((x)->u.rcqe.msn))
232
233/* used for SQ completion processing */
234#define CQE_WRID_SQ_IDX(x) ((x)->u.scqe.cidx)
175 u16 nada2;
176 u16 cidx;
177 } scqe;
178 struct {
179 __be32 wrid_hi;
180 __be32 wrid_low;
181 } gen;
182 } u;

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228#define CQE_LEN(x) (be32_to_cpu((x)->len))
229
230/* used for RQ completion processing */
231#define CQE_WRID_STAG(x) (be32_to_cpu((x)->u.rcqe.stag))
232#define CQE_WRID_MSN(x) (be32_to_cpu((x)->u.rcqe.msn))
233
234/* used for SQ completion processing */
235#define CQE_WRID_SQ_IDX(x) ((x)->u.scqe.cidx)
236#define CQE_WRID_FR_STAG(x) (be32_to_cpu((x)->u.scqe.stag))
235
236/* generic accessor macros */
237#define CQE_WRID_HI(x) (be32_to_cpu((x)->u.gen.wrid_hi))
238#define CQE_WRID_LOW(x) (be32_to_cpu((x)->u.gen.wrid_low))
239
240/* macros for flit 3 of the cqe */
241#define CQE_GENBIT_S 63
242#define CQE_GENBIT_M 0x1

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629 }
630}
631
632static inline int t4_valid_cqe(struct t4_cq *cq, struct t4_cqe *cqe)
633{
634 return (CQE_GENBIT(cqe) == cq->gen);
635}
636
237
238/* generic accessor macros */
239#define CQE_WRID_HI(x) (be32_to_cpu((x)->u.gen.wrid_hi))
240#define CQE_WRID_LOW(x) (be32_to_cpu((x)->u.gen.wrid_low))
241
242/* macros for flit 3 of the cqe */
243#define CQE_GENBIT_S 63
244#define CQE_GENBIT_M 0x1

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631 }
632}
633
634static inline int t4_valid_cqe(struct t4_cq *cq, struct t4_cqe *cqe)
635{
636 return (CQE_GENBIT(cqe) == cq->gen);
637}
638
637static inline int t4_cq_notempty(struct t4_cq *cq)
638{
639 return cq->sw_in_use || t4_valid_cqe(cq, &cq->queue[cq->cidx]);
640}
641
642static inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
643{
644 int ret;
645 u16 prev_cidx;
646
647 if (cq->cidx == 0)
648 prev_cidx = cq->size - 1;
649 else

--- 65 unchanged lines hidden --- 		639static inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
640{
641 int ret;
642 u16 prev_cidx;
643
644 if (cq->cidx == 0)
645 prev_cidx = cq->size - 1;
646 else

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