ad7887.c (75bf465f0bc33e9b776a46d6a1b9b990f5fb7c37) ad7887.c (b0ec7a44393e0d7a60878e2f56412072dd992724)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * AD7887 SPI ADC driver
4 *
5 * Copyright 2010-2011 Analog Devices Inc.
6 */
7
8#include <linux/device.h>

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38 AD7887_CH0,
39 AD7887_CH0_CH1,
40 AD7887_CH1,
41};
42
43/**
44 * struct ad7887_chip_info - chip specifc information
45 * @int_vref_mv: the internal reference voltage
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * AD7887 SPI ADC driver
4 *
5 * Copyright 2010-2011 Analog Devices Inc.
6 */
7
8#include <linux/device.h>

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38 AD7887_CH0,
39 AD7887_CH0_CH1,
40 AD7887_CH1,
41};
42
43/**
44 * struct ad7887_chip_info - chip specifc information
45 * @int_vref_mv: the internal reference voltage
46 * @channel: channel specification
46 * @channels: channels specification
47 * @num_channels: number of channels
48 * @dual_channels: channels specification in dual mode
49 * @num_dual_channels: number of channels in dual mode
47 */
48struct ad7887_chip_info {
49 u16 int_vref_mv;
50 */
51struct ad7887_chip_info {
52 u16 int_vref_mv;
50 struct iio_chan_spec channel[3];
53 const struct iio_chan_spec *channels;
54 unsigned int num_channels;
55 const struct iio_chan_spec *dual_channels;
56 unsigned int num_dual_channels;
51};
52
53struct ad7887_state {
54 struct spi_device *spi;
55 const struct ad7887_chip_info *chip_info;
56 struct regulator *reg;
57 struct spi_transfer xfer[4];
58 struct spi_message msg[3];

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178
179 *val2 = chan->scan_type.realbits;
180
181 return IIO_VAL_FRACTIONAL_LOG2;
182 }
183 return -EINVAL;
184}
185
57};
58
59struct ad7887_state {
60 struct spi_device *spi;
61 const struct ad7887_chip_info *chip_info;
62 struct regulator *reg;
63 struct spi_transfer xfer[4];
64 struct spi_message msg[3];

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184
185 *val2 = chan->scan_type.realbits;
186
187 return IIO_VAL_FRACTIONAL_LOG2;
188 }
189 return -EINVAL;
190}
191
192#define AD7887_CHANNEL(x) { \
193 .type = IIO_VOLTAGE, \
194 .indexed = 1, \
195 .channel = (x), \
196 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
197 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
198 .address = (x), \
199 .scan_index = (x), \
200 .scan_type = { \
201 .sign = 'u', \
202 .realbits = 12, \
203 .storagebits = 16, \
204 .shift = 0, \
205 .endianness = IIO_BE, \
206 }, \
207}
186
208
209static const struct iio_chan_spec ad7887_channels[] = {
210 AD7887_CHANNEL(0),
211 IIO_CHAN_SOFT_TIMESTAMP(1),
212};
213
214static const struct iio_chan_spec ad7887_dual_channels[] = {
215 AD7887_CHANNEL(0),
216 AD7887_CHANNEL(1),
217 IIO_CHAN_SOFT_TIMESTAMP(2),
218};
219
187static const struct ad7887_chip_info ad7887_chip_info_tbl[] = {
188 /*
189 * More devices added in future
190 */
191 [ID_AD7887] = {
220static const struct ad7887_chip_info ad7887_chip_info_tbl[] = {
221 /*
222 * More devices added in future
223 */
224 [ID_AD7887] = {
192 .channel[0] = {
193 .type = IIO_VOLTAGE,
194 .indexed = 1,
195 .channel = 1,
196 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
197 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
198 .address = 1,
199 .scan_index = 1,
200 .scan_type = {
201 .sign = 'u',
202 .realbits = 12,
203 .storagebits = 16,
204 .shift = 0,
205 .endianness = IIO_BE,
206 },
207 },
208 .channel[1] = {
209 .type = IIO_VOLTAGE,
210 .indexed = 1,
211 .channel = 0,
212 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
213 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
214 .address = 0,
215 .scan_index = 0,
216 .scan_type = {
217 .sign = 'u',
218 .realbits = 12,
219 .storagebits = 16,
220 .shift = 0,
221 .endianness = IIO_BE,
222 },
223 },
224 .channel[2] = IIO_CHAN_SOFT_TIMESTAMP(2),
225 .channels = ad7887_channels,
226 .num_channels = ARRAY_SIZE(ad7887_channels),
227 .dual_channels = ad7887_dual_channels,
228 .num_dual_channels = ARRAY_SIZE(ad7887_dual_channels),
225 .int_vref_mv = 2500,
226 },
227};
228
229static const struct iio_info ad7887_info = {
230 .read_raw = &ad7887_read_raw,
231};
232

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301
302 st->xfer[3].rx_buf = &st->data[2];
303 st->xfer[3].tx_buf = &st->tx_cmd_buf[2];
304 st->xfer[3].len = 2;
305
306 spi_message_init(&st->msg[AD7887_CH1]);
307 spi_message_add_tail(&st->xfer[3], &st->msg[AD7887_CH1]);
308
229 .int_vref_mv = 2500,
230 },
231};
232
233static const struct iio_info ad7887_info = {
234 .read_raw = &ad7887_read_raw,
235};
236

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305
306 st->xfer[3].rx_buf = &st->data[2];
307 st->xfer[3].tx_buf = &st->tx_cmd_buf[2];
308 st->xfer[3].len = 2;
309
310 spi_message_init(&st->msg[AD7887_CH1]);
311 spi_message_add_tail(&st->xfer[3], &st->msg[AD7887_CH1]);
312
309 indio_dev->channels = st->chip_info->channel;
310 indio_dev->num_channels = 3;
313 indio_dev->channels = st->chip_info->dual_channels;
314 indio_dev->num_channels = st->chip_info->num_dual_channels;
311 } else {
315 } else {
312 indio_dev->channels = &st->chip_info->channel[1];
313 indio_dev->num_channels = 2;
316 indio_dev->channels = st->chip_info->channels;
317 indio_dev->num_channels = st->chip_info->num_channels;
314 }
315
316 ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
317 &ad7887_trigger_handler, &ad7887_ring_setup_ops);
318 if (ret)
319 goto error_disable_reg;
320
321 ret = iio_device_register(indio_dev);

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319
320 ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
321 &ad7887_trigger_handler, &ad7887_ring_setup_ops);
322 if (ret)
323 goto error_disable_reg;
324
325 ret = iio_device_register(indio_dev);

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