ad7192.c (651a88798412e216f337d70181127e847f00a4b7) ad7192.c (74f582ec127e3b10aec71e8d15f1c14b0f0481ec)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * AD7190 AD7192 AD7193 AD7195 SPI ADC driver
4 *
5 * Copyright 2011-2015 Analog Devices Inc.
6 */
7
8#include <linux/interrupt.h>

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53#define AD7192_STAT_PARITY BIT(4) /* Parity */
54#define AD7192_STAT_CH3 BIT(2) /* Channel 3 */
55#define AD7192_STAT_CH2 BIT(1) /* Channel 2 */
56#define AD7192_STAT_CH1 BIT(0) /* Channel 1 */
57
58/* Mode Register Bit Designations (AD7192_REG_MODE) */
59#define AD7192_MODE_SEL(x) (((x) & 0x7) << 21) /* Operation Mode Select */
60#define AD7192_MODE_SEL_MASK (0x7 << 21) /* Operation Mode Select Mask */
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * AD7190 AD7192 AD7193 AD7195 SPI ADC driver
4 *
5 * Copyright 2011-2015 Analog Devices Inc.
6 */
7
8#include <linux/interrupt.h>

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53#define AD7192_STAT_PARITY BIT(4) /* Parity */
54#define AD7192_STAT_CH3 BIT(2) /* Channel 3 */
55#define AD7192_STAT_CH2 BIT(1) /* Channel 2 */
56#define AD7192_STAT_CH1 BIT(0) /* Channel 1 */
57
58/* Mode Register Bit Designations (AD7192_REG_MODE) */
59#define AD7192_MODE_SEL(x) (((x) & 0x7) << 21) /* Operation Mode Select */
60#define AD7192_MODE_SEL_MASK (0x7 << 21) /* Operation Mode Select Mask */
61#define AD7192_MODE_DAT_STA BIT(20) /* Status Register transmission */
61#define AD7192_MODE_STA(x) (((x) & 0x1) << 20) /* Status Register transmission */
62#define AD7192_MODE_STA_MASK BIT(20) /* Status Register transmission Mask */
62#define AD7192_MODE_CLKSRC(x) (((x) & 0x3) << 18) /* Clock Source Select */
63#define AD7192_MODE_SINC3 BIT(15) /* SINC3 Filter Select */
64#define AD7192_MODE_ACX BIT(14) /* AC excitation enable(AD7195 only)*/
65#define AD7192_MODE_ENPAR BIT(13) /* Parity Enable */
66#define AD7192_MODE_CLKDIV BIT(12) /* Clock divide by 2 (AD7190/2 only)*/
67#define AD7192_MODE_SCYCLE BIT(11) /* Single cycle conversion */
68#define AD7192_MODE_REJ60 BIT(10) /* 50/60Hz notch filter */
69#define AD7192_MODE_RATE(x) ((x) & 0x3FF) /* Filter Update Rate Select */

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220 uintptr_t private,
221 const struct iio_chan_spec *chan,
222 const char *buf, size_t len)
223{
224 struct ad7192_state *st = iio_priv(indio_dev);
225 bool sys_calib;
226 int ret, temp;
227
63#define AD7192_MODE_CLKSRC(x) (((x) & 0x3) << 18) /* Clock Source Select */
64#define AD7192_MODE_SINC3 BIT(15) /* SINC3 Filter Select */
65#define AD7192_MODE_ACX BIT(14) /* AC excitation enable(AD7195 only)*/
66#define AD7192_MODE_ENPAR BIT(13) /* Parity Enable */
67#define AD7192_MODE_CLKDIV BIT(12) /* Clock divide by 2 (AD7190/2 only)*/
68#define AD7192_MODE_SCYCLE BIT(11) /* Single cycle conversion */
69#define AD7192_MODE_REJ60 BIT(10) /* 50/60Hz notch filter */
70#define AD7192_MODE_RATE(x) ((x) & 0x3FF) /* Filter Update Rate Select */

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221 uintptr_t private,
222 const struct iio_chan_spec *chan,
223 const char *buf, size_t len)
224{
225 struct ad7192_state *st = iio_priv(indio_dev);
226 bool sys_calib;
227 int ret, temp;
228
228 ret = strtobool(buf, &sys_calib);
229 ret = kstrtobool(buf, &sys_calib);
229 if (ret)
230 return ret;
231
232 temp = st->syscalib_mode[chan->channel];
233 if (sys_calib) {
234 if (temp == AD7192_SYSCALIB_ZERO_SCALE)
235 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_ZERO,
236 chan->address);

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283 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
284
285 st->mode &= ~AD7192_MODE_SEL_MASK;
286 st->mode |= AD7192_MODE_SEL(mode);
287
288 return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
289}
290
230 if (ret)
231 return ret;
232
233 temp = st->syscalib_mode[chan->channel];
234 if (sys_calib) {
235 if (temp == AD7192_SYSCALIB_ZERO_SCALE)
236 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_ZERO,
237 chan->address);

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284 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
285
286 st->mode &= ~AD7192_MODE_SEL_MASK;
287 st->mode |= AD7192_MODE_SEL(mode);
288
289 return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
290}
291
292static int ad7192_append_status(struct ad_sigma_delta *sd, bool append)
293{
294 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
295 unsigned int mode = st->mode;
296 int ret;
297
298 mode &= ~AD7192_MODE_STA_MASK;
299 mode |= AD7192_MODE_STA(append);
300
301 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, mode);
302 if (ret < 0)
303 return ret;
304
305 st->mode = mode;
306
307 return 0;
308}
309
310static int ad7192_disable_all(struct ad_sigma_delta *sd)
311{
312 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
313 u32 conf = st->conf;
314 int ret;
315
316 conf &= ~AD7192_CONF_CHAN_MASK;
317
318 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf);
319 if (ret < 0)
320 return ret;
321
322 st->conf = conf;
323
324 return 0;
325}
326
291static const struct ad_sigma_delta_info ad7192_sigma_delta_info = {
292 .set_channel = ad7192_set_channel,
327static const struct ad_sigma_delta_info ad7192_sigma_delta_info = {
328 .set_channel = ad7192_set_channel,
329 .append_status = ad7192_append_status,
330 .disable_all = ad7192_disable_all,
293 .set_mode = ad7192_set_mode,
294 .has_registers = true,
295 .addr_shift = 3,
296 .read_mask = BIT(6),
331 .set_mode = ad7192_set_mode,
332 .has_registers = true,
333 .addr_shift = 3,
334 .read_mask = BIT(6),
335 .status_ch_mask = GENMASK(3, 0),
336 .num_slots = 4,
297 .irq_flags = IRQF_TRIGGER_FALLING,
298};
299
300static const struct ad_sd_calib_data ad7192_calib_arr[8] = {
301 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1},
302 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1},
303 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2},
304 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2},

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452 size_t len)
453{
454 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
455 struct ad7192_state *st = iio_priv(indio_dev);
456 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
457 int ret;
458 bool val;
459
337 .irq_flags = IRQF_TRIGGER_FALLING,
338};
339
340static const struct ad_sd_calib_data ad7192_calib_arr[8] = {
341 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1},
342 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1},
343 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2},
344 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2},

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492 size_t len)
493{
494 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
495 struct ad7192_state *st = iio_priv(indio_dev);
496 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
497 int ret;
498 bool val;
499
460 ret = strtobool(buf, &val);
500 ret = kstrtobool(buf, &val);
461 if (ret < 0)
462 return ret;
463
464 ret = iio_device_claim_direct_mode(indio_dev);
465 if (ret)
466 return ret;
467
468 switch ((u32)this_attr->address) {

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778 *length = ARRAY_SIZE(st->scale_avail) * 2;
779
780 return IIO_AVAIL_LIST;
781 }
782
783 return -EINVAL;
784}
785
501 if (ret < 0)
502 return ret;
503
504 ret = iio_device_claim_direct_mode(indio_dev);
505 if (ret)
506 return ret;
507
508 switch ((u32)this_attr->address) {

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818 *length = ARRAY_SIZE(st->scale_avail) * 2;
819
820 return IIO_AVAIL_LIST;
821 }
822
823 return -EINVAL;
824}
825
826static int ad7192_update_scan_mode(struct iio_dev *indio_dev, const unsigned long *scan_mask)
827{
828 struct ad7192_state *st = iio_priv(indio_dev);
829 u32 conf = st->conf;
830 int ret;
831 int i;
832
833 conf &= ~AD7192_CONF_CHAN_MASK;
834 for_each_set_bit(i, scan_mask, 8)
835 conf |= AD7192_CONF_CHAN(i);
836
837 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf);
838 if (ret < 0)
839 return ret;
840
841 st->conf = conf;
842
843 return 0;
844}
845
786static const struct iio_info ad7192_info = {
787 .read_raw = ad7192_read_raw,
788 .write_raw = ad7192_write_raw,
789 .write_raw_get_fmt = ad7192_write_raw_get_fmt,
790 .read_avail = ad7192_read_avail,
791 .attrs = &ad7192_attribute_group,
792 .validate_trigger = ad_sd_validate_trigger,
846static const struct iio_info ad7192_info = {
847 .read_raw = ad7192_read_raw,
848 .write_raw = ad7192_write_raw,
849 .write_raw_get_fmt = ad7192_write_raw_get_fmt,
850 .read_avail = ad7192_read_avail,
851 .attrs = &ad7192_attribute_group,
852 .validate_trigger = ad_sd_validate_trigger,
853 .update_scan_mode = ad7192_update_scan_mode,
793};
794
795static const struct iio_info ad7195_info = {
796 .read_raw = ad7192_read_raw,
797 .write_raw = ad7192_write_raw,
798 .write_raw_get_fmt = ad7192_write_raw_get_fmt,
799 .read_avail = ad7192_read_avail,
800 .attrs = &ad7195_attribute_group,
801 .validate_trigger = ad_sd_validate_trigger,
854};
855
856static const struct iio_info ad7195_info = {
857 .read_raw = ad7192_read_raw,
858 .write_raw = ad7192_write_raw,
859 .write_raw_get_fmt = ad7192_write_raw_get_fmt,
860 .read_avail = ad7192_read_avail,
861 .attrs = &ad7195_attribute_group,
862 .validate_trigger = ad_sd_validate_trigger,
863 .update_scan_mode = ad7192_update_scan_mode,
802};
803
804#define __AD719x_CHANNEL(_si, _channel1, _channel2, _address, _extend_name, \
805 _type, _mask_type_av, _ext_info) \
806 { \
807 .type = (_type), \
808 .differential = ((_channel2) == -1 ? 0 : 1), \
809 .indexed = 1, \

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865
866#define __AD719x_CHANNEL(_si, _channel1, _channel2, _address, _extend_name, \
867 _type, _mask_type_av, _ext_info) \
868 { \
869 .type = (_type), \
870 .differential = ((_channel2) == -1 ? 0 : 1), \
871 .indexed = 1, \

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