jc42.c (032c1623c9de51705d0a1c577ffdae746967e88d) jc42.c (c7250b5d553cae39bdfcac95ef5bdac6f6a5b022)
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * jc42.c - driver for Jedec JC42.4 compliant temperature sensors
4 *
5 * Copyright (c) 2010 Ericsson AB.
6 *
7 * Derived from lm77.c by Andras BALI <drewie@freemail.hu>.
8 *

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58#define MAX_MANID 0x004d /* Maxim */
59#define IDT_MANID 0x00b3 /* IDT */
60#define MCP_MANID 0x0054 /* Microchip */
61#define NXP_MANID 0x1131 /* NXP Semiconductors */
62#define ONS_MANID 0x1b09 /* ON Semiconductor */
63#define STM_MANID 0x104a /* ST Microelectronics */
64#define GT_MANID 0x1c68 /* Giantec */
65#define GT_MANID2 0x132d /* Giantec, 2nd mfg ID */
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * jc42.c - driver for Jedec JC42.4 compliant temperature sensors
4 *
5 * Copyright (c) 2010 Ericsson AB.
6 *
7 * Derived from lm77.c by Andras BALI <drewie@freemail.hu>.
8 *

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58#define MAX_MANID 0x004d /* Maxim */
59#define IDT_MANID 0x00b3 /* IDT */
60#define MCP_MANID 0x0054 /* Microchip */
61#define NXP_MANID 0x1131 /* NXP Semiconductors */
62#define ONS_MANID 0x1b09 /* ON Semiconductor */
63#define STM_MANID 0x104a /* ST Microelectronics */
64#define GT_MANID 0x1c68 /* Giantec */
65#define GT_MANID2 0x132d /* Giantec, 2nd mfg ID */
66#define SI_MANID 0x1c85 /* Seiko Instruments */
66
67/* SMBUS register */
68#define SMBUS_STMOUT BIT(7) /* SMBus time-out, active low */
69
70/* Supported chips */
71
72/* Analog Devices */
73#define ADT7408_DEVID 0x0801

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151#define STTS2002_DEVID_MASK 0xffff
152
153#define STTS2004_DEVID 0x2201
154#define STTS2004_DEVID_MASK 0xffff
155
156#define STTS3000_DEVID 0x0200
157#define STTS3000_DEVID_MASK 0xffff
158
67
68/* SMBUS register */
69#define SMBUS_STMOUT BIT(7) /* SMBus time-out, active low */
70
71/* Supported chips */
72
73/* Analog Devices */
74#define ADT7408_DEVID 0x0801

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152#define STTS2002_DEVID_MASK 0xffff
153
154#define STTS2004_DEVID 0x2201
155#define STTS2004_DEVID_MASK 0xffff
156
157#define STTS3000_DEVID 0x0200
158#define STTS3000_DEVID_MASK 0xffff
159
160/* Seiko Instruments */
161#define S34TS04A_DEVID 0x2221
162#define S34TS04A_DEVID_MASK 0xffff
163
159static u16 jc42_hysteresis[] = { 0, 1500, 3000, 6000 };
160
161struct jc42_chips {
162 u16 manid;
163 u16 devid;
164 u16 devid_mask;
165};
166

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181 { MCP_MANID, MCP98244_DEVID, MCP98244_DEVID_MASK },
182 { MCP_MANID, MCP9843_DEVID, MCP9843_DEVID_MASK },
183 { NXP_MANID, SE97_DEVID, SE97_DEVID_MASK },
184 { ONS_MANID, CAT6095_DEVID, CAT6095_DEVID_MASK },
185 { ONS_MANID, CAT34TS02C_DEVID, CAT34TS02C_DEVID_MASK },
186 { ONS_MANID, CAT34TS04_DEVID, CAT34TS04_DEVID_MASK },
187 { ONS_MANID, N34TS04_DEVID, N34TS04_DEVID_MASK },
188 { NXP_MANID, SE98_DEVID, SE98_DEVID_MASK },
164static u16 jc42_hysteresis[] = { 0, 1500, 3000, 6000 };
165
166struct jc42_chips {
167 u16 manid;
168 u16 devid;
169 u16 devid_mask;
170};
171

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186 { MCP_MANID, MCP98244_DEVID, MCP98244_DEVID_MASK },
187 { MCP_MANID, MCP9843_DEVID, MCP9843_DEVID_MASK },
188 { NXP_MANID, SE97_DEVID, SE97_DEVID_MASK },
189 { ONS_MANID, CAT6095_DEVID, CAT6095_DEVID_MASK },
190 { ONS_MANID, CAT34TS02C_DEVID, CAT34TS02C_DEVID_MASK },
191 { ONS_MANID, CAT34TS04_DEVID, CAT34TS04_DEVID_MASK },
192 { ONS_MANID, N34TS04_DEVID, N34TS04_DEVID_MASK },
193 { NXP_MANID, SE98_DEVID, SE98_DEVID_MASK },
194 { SI_MANID, S34TS04A_DEVID, S34TS04A_DEVID_MASK },
189 { STM_MANID, STTS424_DEVID, STTS424_DEVID_MASK },
190 { STM_MANID, STTS424E_DEVID, STTS424E_DEVID_MASK },
191 { STM_MANID, STTS2002_DEVID, STTS2002_DEVID_MASK },
192 { STM_MANID, STTS2004_DEVID, STTS2004_DEVID_MASK },
193 { STM_MANID, STTS3000_DEVID, STTS3000_DEVID_MASK },
194};
195
196enum temp_index {

--- 405 unchanged lines hidden --- 		195 { STM_MANID, STTS424_DEVID, STTS424_DEVID_MASK },
196 { STM_MANID, STTS424E_DEVID, STTS424E_DEVID_MASK },
197 { STM_MANID, STTS2002_DEVID, STTS2002_DEVID_MASK },
198 { STM_MANID, STTS2004_DEVID, STTS2004_DEVID_MASK },
199 { STM_MANID, STTS3000_DEVID, STTS3000_DEVID_MASK },
200};
201
202enum temp_index {

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