it87.c (dca3a783400a18e2bf4503b1d4a85c4d0ca1a7e4) it87.c (088ce2ac9ebac5c74faf4d39083627875fa6f0f0)
1/*
2 * it87.c - Part of lm_sensors, Linux kernel modules for hardware
3 * monitoring.
4 *
5 * The IT8705F is an LPC-based Super I/O part that contains UARTs, a
6 * parallel port, an IR port, a MIDI port, a floppy controller, etc., in
7 * addition to an Environment Controller (Enhanced Hardware Monitor and
8 * Fan Controller)

--- 1764 unchanged lines hidden (view full) ---

1773 if (sio_data->type == it87) {
1774 /* The IT8705F doesn't have VID pins at all */
1775 sio_data->skip_vid = 1;
1776
1777 /* The IT8705F has a different LD number for GPIO */
1778 superio_select(5);
1779 sio_data->beep_pin = superio_inb(IT87_SIO_BEEP_PIN_REG) & 0x3f;
1780 } else if (sio_data->type == it8783) {
1/*
2 * it87.c - Part of lm_sensors, Linux kernel modules for hardware
3 * monitoring.
4 *
5 * The IT8705F is an LPC-based Super I/O part that contains UARTs, a
6 * parallel port, an IR port, a MIDI port, a floppy controller, etc., in
7 * addition to an Environment Controller (Enhanced Hardware Monitor and
8 * Fan Controller)

--- 1764 unchanged lines hidden (view full) ---

1773 if (sio_data->type == it87) {
1774 /* The IT8705F doesn't have VID pins at all */
1775 sio_data->skip_vid = 1;
1776
1777 /* The IT8705F has a different LD number for GPIO */
1778 superio_select(5);
1779 sio_data->beep_pin = superio_inb(IT87_SIO_BEEP_PIN_REG) & 0x3f;
1780 } else if (sio_data->type == it8783) {
1781 int reg25, reg27, reg2A, reg2C, regEF;
1781 int reg25, reg27, reg2a, reg2c, regef;
1782
1783 sio_data->skip_vid = 1; /* No VID */
1784
1785 superio_select(GPIO);
1786
1787 reg25 = superio_inb(IT87_SIO_GPIO1_REG);
1788 reg27 = superio_inb(IT87_SIO_GPIO3_REG);
1782
1783 sio_data->skip_vid = 1; /* No VID */
1784
1785 superio_select(GPIO);
1786
1787 reg25 = superio_inb(IT87_SIO_GPIO1_REG);
1788 reg27 = superio_inb(IT87_SIO_GPIO3_REG);
1789 reg2A = superio_inb(IT87_SIO_PINX1_REG);
1790 reg2C = superio_inb(IT87_SIO_PINX2_REG);
1791 regEF = superio_inb(IT87_SIO_SPI_REG);
1789 reg2a = superio_inb(IT87_SIO_PINX1_REG);
1790 reg2c = superio_inb(IT87_SIO_PINX2_REG);
1791 regef = superio_inb(IT87_SIO_SPI_REG);
1792
1793 /* Check if fan3 is there or not */
1792
1793 /* Check if fan3 is there or not */
1794 if ((reg27 & (1 << 0)) || !(reg2C & (1 << 2)))
1794 if ((reg27 & (1 << 0)) || !(reg2c & (1 << 2)))
1795 sio_data->skip_fan |= (1 << 2);
1796 if ((reg25 & (1 << 4))
1795 sio_data->skip_fan |= (1 << 2);
1796 if ((reg25 & (1 << 4))
1797 || (!(reg2A & (1 << 1)) && (regEF & (1 << 0))))
1797 || (!(reg2a & (1 << 1)) && (regef & (1 << 0))))
1798 sio_data->skip_pwm |= (1 << 2);
1799
1800 /* Check if fan2 is there or not */
1801 if (reg27 & (1 << 7))
1802 sio_data->skip_fan |= (1 << 1);
1803 if (reg27 & (1 << 3))
1804 sio_data->skip_pwm |= (1 << 1);
1805
1806 /* VIN5 */
1798 sio_data->skip_pwm |= (1 << 2);
1799
1800 /* Check if fan2 is there or not */
1801 if (reg27 & (1 << 7))
1802 sio_data->skip_fan |= (1 << 1);
1803 if (reg27 & (1 << 3))
1804 sio_data->skip_pwm |= (1 << 1);
1805
1806 /* VIN5 */
1807 if ((reg27 & (1 << 0)) || (reg2C & (1 << 2)))
1807 if ((reg27 & (1 << 0)) || (reg2c & (1 << 2)))
1808 sio_data->skip_in |= (1 << 5); /* No VIN5 */
1809
1810 /* VIN6 */
1811 if (reg27 & (1 << 1))
1812 sio_data->skip_in |= (1 << 6); /* No VIN6 */
1813
1814 /*
1815 * VIN7

--- 8 unchanged lines hidden (view full) ---

1824 * This is different to other chips, where the internal
1825 * voltage divider would connect VIN7 to an internal
1826 * voltage source. Maybe that is the case here as well.
1827 *
1828 * Since we don't know for sure, re-route it if that is
1829 * not the case, and ask the user to report if the
1830 * resulting voltage is sane.
1831 */
1808 sio_data->skip_in |= (1 << 5); /* No VIN5 */
1809
1810 /* VIN6 */
1811 if (reg27 & (1 << 1))
1812 sio_data->skip_in |= (1 << 6); /* No VIN6 */
1813
1814 /*
1815 * VIN7

--- 8 unchanged lines hidden (view full) ---

1824 * This is different to other chips, where the internal
1825 * voltage divider would connect VIN7 to an internal
1826 * voltage source. Maybe that is the case here as well.
1827 *
1828 * Since we don't know for sure, re-route it if that is
1829 * not the case, and ask the user to report if the
1830 * resulting voltage is sane.
1831 */
1832 if (!(reg2C & (1 << 1))) {
1833 reg2C |= (1 << 1);
1834 superio_outb(IT87_SIO_PINX2_REG, reg2C);
1832 if (!(reg2c & (1 << 1))) {
1833 reg2c |= (1 << 1);
1834 superio_outb(IT87_SIO_PINX2_REG, reg2c);
1835 pr_notice("Routing internal VCCH5V to in7.\n");
1836 }
1837 pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
1838 pr_notice("Please report if it displays a reasonable voltage.\n");
1839 }
1840
1835 pr_notice("Routing internal VCCH5V to in7.\n");
1836 }
1837 pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
1838 pr_notice("Please report if it displays a reasonable voltage.\n");
1839 }
1840
1841 if (reg2C & (1 << 0))
1841 if (reg2c & (1 << 0))
1842 sio_data->internal |= (1 << 0);
1842 sio_data->internal |= (1 << 0);
1843 if (reg2C & (1 << 1))
1843 if (reg2c & (1 << 1))
1844 sio_data->internal |= (1 << 1);
1845
1846 sio_data->beep_pin = superio_inb(IT87_SIO_BEEP_PIN_REG) & 0x3f;
1847
1848 } else {
1849 int reg;
1850 bool uart6;
1851

--- 782 unchanged lines hidden --- 		1844 sio_data->internal |= (1 << 1);
1845
1846 sio_data->beep_pin = superio_inb(IT87_SIO_BEEP_PIN_REG) & 0x3f;
1847
1848 } else {
1849 int reg;
1850 bool uart6;
1851

--- 782 unchanged lines hidden ---