ads7871.c (688d794c4c3f8b08c814381ee2edd3ede5856056) ads7871.c (088ce2ac9ebac5c74faf4d39083627875fa6f0f0)
1/*
2 * ads7871 - driver for TI ADS7871 A/D converter
3 *
4 * Copyright (c) 2010 Paul Thomas <pthomas8589@gmail.com>
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

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35#define REG_ID 31 /*ID Register*/
36
37/*
38 * From figure 17 in the datasheet
39 * These bits get ORed with the address to form
40 * the instruction byte
41 */
42/*Instruction Bit masks*/
1/*
2 * ads7871 - driver for TI ADS7871 A/D converter
3 *
4 * Copyright (c) 2010 Paul Thomas <pthomas8589@gmail.com>
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

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35#define REG_ID 31 /*ID Register*/
36
37/*
38 * From figure 17 in the datasheet
39 * These bits get ORed with the address to form
40 * the instruction byte
41 */
42/*Instruction Bit masks*/
43#define INST_MODE_bm (1<<7)
44#define INST_READ_bm (1<<6)
45#define INST_16BIT_bm (1<<5)
43#define INST_MODE_BM (1 << 7)
44#define INST_READ_BM (1 << 6)
45#define INST_16BIT_BM (1 << 5)
46
47/*From figure 18 in the datasheet*/
48/*bit masks for Rev/Oscillator Control Register*/
46
47/*From figure 18 in the datasheet*/
48/*bit masks for Rev/Oscillator Control Register*/
49#define MUX_CNV_bv 7
50#define MUX_CNV_bm (1<<MUX_CNV_bv)
51#define MUX_M3_bm (1<<3) /*M3 selects single ended*/
52#define MUX_G_bv 4 /*allows for reg = (gain << MUX_G_bv) | ...*/
49#define MUX_CNV_BV 7
50#define MUX_CNV_BM (1 << MUX_CNV_BV)
51#define MUX_M3_BM (1 << 3) /*M3 selects single ended*/
52#define MUX_G_BV 4 /*allows for reg = (gain << MUX_G_BV) | ...*/
53
54/*From figure 18 in the datasheet*/
55/*bit masks for Rev/Oscillator Control Register*/
53
54/*From figure 18 in the datasheet*/
55/*bit masks for Rev/Oscillator Control Register*/
56#define OSC_OSCR_bm (1<<5)
57#define OSC_OSCE_bm (1<<4)
58#define OSC_REFE_bm (1<<3)
59#define OSC_BUFE_bm (1<<2)
60#define OSC_R2V_bm (1<<1)
61#define OSC_RBG_bm (1<<0)
56#define OSC_OSCR_BM (1 << 5)
57#define OSC_OSCE_BM (1 << 4)
58#define OSC_REFE_BM (1 << 3)
59#define OSC_BUFE_BM (1 << 2)
60#define OSC_R2V_BM (1 << 1)
61#define OSC_RBG_BM (1 << 0)
62
63#include <linux/module.h>
64#include <linux/init.h>
65#include <linux/spi/spi.h>
66#include <linux/hwmon.h>
67#include <linux/hwmon-sysfs.h>
68#include <linux/err.h>
69#include <linux/mutex.h>

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74struct ads7871_data {
75 struct device *hwmon_dev;
76 struct mutex update_lock;
77};
78
79static int ads7871_read_reg8(struct spi_device *spi, int reg)
80{
81 int ret;
62
63#include <linux/module.h>
64#include <linux/init.h>
65#include <linux/spi/spi.h>
66#include <linux/hwmon.h>
67#include <linux/hwmon-sysfs.h>
68#include <linux/err.h>
69#include <linux/mutex.h>

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74struct ads7871_data {
75 struct device *hwmon_dev;
76 struct mutex update_lock;
77};
78
79static int ads7871_read_reg8(struct spi_device *spi, int reg)
80{
81 int ret;
82 reg = reg | INST_READ_bm;
82 reg = reg | INST_READ_BM;
83 ret = spi_w8r8(spi, reg);
84 return ret;
85}
86
87static int ads7871_read_reg16(struct spi_device *spi, int reg)
88{
89 int ret;
83 ret = spi_w8r8(spi, reg);
84 return ret;
85}
86
87static int ads7871_read_reg16(struct spi_device *spi, int reg)
88{
89 int ret;
90 reg = reg | INST_READ_bm | INST_16BIT_bm;
90 reg = reg | INST_READ_BM | INST_16BIT_BM;
91 ret = spi_w8r16(spi, reg);
92 return ret;
93}
94
95static int ads7871_write_reg8(struct spi_device *spi, int reg, u8 val)
96{
97 u8 tmp[2] = {reg, val};
98 return spi_write(spi, tmp, sizeof(tmp));

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106 int ret, val, i = 0;
107 uint8_t channel, mux_cnv;
108
109 channel = attr->index;
110 /*
111 * TODO: add support for conversions
112 * other than single ended with a gain of 1
113 */
91 ret = spi_w8r16(spi, reg);
92 return ret;
93}
94
95static int ads7871_write_reg8(struct spi_device *spi, int reg, u8 val)
96{
97 u8 tmp[2] = {reg, val};
98 return spi_write(spi, tmp, sizeof(tmp));

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106 int ret, val, i = 0;
107 uint8_t channel, mux_cnv;
108
109 channel = attr->index;
110 /*
111 * TODO: add support for conversions
112 * other than single ended with a gain of 1
113 */
114 /*MUX_M3_bm forces single ended*/
114 /*MUX_M3_BM forces single ended*/
115 /*This is also where the gain of the PGA would be set*/
116 ads7871_write_reg8(spi, REG_GAIN_MUX,
115 /*This is also where the gain of the PGA would be set*/
116 ads7871_write_reg8(spi, REG_GAIN_MUX,
117 (MUX_CNV_bm | MUX_M3_bm | channel));
117 (MUX_CNV_BM | MUX_M3_BM | channel));
118
119 ret = ads7871_read_reg8(spi, REG_GAIN_MUX);
118
119 ret = ads7871_read_reg8(spi, REG_GAIN_MUX);
120 mux_cnv = ((ret & MUX_CNV_bm)>>MUX_CNV_bv);
120 mux_cnv = ((ret & MUX_CNV_BM) >> MUX_CNV_BV);
121 /*
122 * on 400MHz arm9 platform the conversion
123 * is already done when we do this test
124 */
125 while ((i < 2) && mux_cnv) {
126 i++;
127 ret = ads7871_read_reg8(spi, REG_GAIN_MUX);
121 /*
122 * on 400MHz arm9 platform the conversion
123 * is already done when we do this test
124 */
125 while ((i < 2) && mux_cnv) {
126 i++;
127 ret = ads7871_read_reg8(spi, REG_GAIN_MUX);
128 mux_cnv = ((ret & MUX_CNV_bm)>>MUX_CNV_bv);
128 mux_cnv = ((ret & MUX_CNV_BM) >> MUX_CNV_BV);
129 msleep_interruptible(1);
130 }
131
132 if (mux_cnv == 0) {
133 val = ads7871_read_reg16(spi, REG_LS_BYTE);
134 /*result in volts*10000 = (val/8192)*2.5*10000*/
129 msleep_interruptible(1);
130 }
131
132 if (mux_cnv == 0) {
133 val = ads7871_read_reg16(spi, REG_LS_BYTE);
134 /*result in volts*10000 = (val/8192)*2.5*10000*/
135 val = ((val>>2) * 25000) / 8192;
135 val = ((val >> 2) * 25000) / 8192;
136 return sprintf(buf, "%d\n", val);
137 } else {
138 return -1;
139 }
140}
141
142static ssize_t ads7871_show_name(struct device *dev,
143 struct device_attribute *devattr, char *buf)

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184 /* Configure the SPI bus */
185 spi->mode = (SPI_MODE_0);
186 spi->bits_per_word = 8;
187 spi_setup(spi);
188
189 ads7871_write_reg8(spi, REG_SER_CONTROL, 0);
190 ads7871_write_reg8(spi, REG_AD_CONTROL, 0);
191
136 return sprintf(buf, "%d\n", val);
137 } else {
138 return -1;
139 }
140}
141
142static ssize_t ads7871_show_name(struct device *dev,
143 struct device_attribute *devattr, char *buf)

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184 /* Configure the SPI bus */
185 spi->mode = (SPI_MODE_0);
186 spi->bits_per_word = 8;
187 spi_setup(spi);
188
189 ads7871_write_reg8(spi, REG_SER_CONTROL, 0);
190 ads7871_write_reg8(spi, REG_AD_CONTROL, 0);
191
192 val = (OSC_OSCR_bm | OSC_OSCE_bm | OSC_REFE_bm | OSC_BUFE_bm);
192 val = (OSC_OSCR_BM | OSC_OSCE_BM | OSC_REFE_BM | OSC_BUFE_BM);
193 ads7871_write_reg8(spi, REG_OSC_CONTROL, val);
194 ret = ads7871_read_reg8(spi, REG_OSC_CONTROL);
195
196 dev_dbg(&spi->dev, "REG_OSC_CONTROL write:%x, read:%x\n", val, ret);
197 /*
198 * because there is no other error checking on an SPI bus
199 * we need to make sure we really have a chip
200 */

--- 51 unchanged lines hidden --- 		193 ads7871_write_reg8(spi, REG_OSC_CONTROL, val);
194 ret = ads7871_read_reg8(spi, REG_OSC_CONTROL);
195
196 dev_dbg(&spi->dev, "REG_OSC_CONTROL write:%x, read:%x\n", val, ret);
197 /*
198 * because there is no other error checking on an SPI bus
199 * we need to make sure we really have a chip
200 */

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