hte-tegra194.c (4f2c0a4acffbec01079c28f839422e64ddeff004) hte-tegra194.c (b003fb5c9df8a8923bf46e0c00cc54edcfb0fbe3)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2021-2022 NVIDIA Corporation
4 *
5 * Author: Dipen Patel <dipenp@nvidia.com>
6 */
7
8#include <linux/err.h>

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57#define NV_AON_HTE_SLICE2_IRQ_GPIO_20 20
58#define NV_AON_HTE_SLICE2_IRQ_GPIO_21 21
59#define NV_AON_HTE_SLICE2_IRQ_GPIO_22 22
60#define NV_AON_HTE_SLICE2_IRQ_GPIO_23 23
61#define NV_AON_HTE_SLICE2_IRQ_GPIO_24 24
62#define NV_AON_HTE_SLICE2_IRQ_GPIO_25 25
63#define NV_AON_HTE_SLICE2_IRQ_GPIO_26 26
64#define NV_AON_HTE_SLICE2_IRQ_GPIO_27 27
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2021-2022 NVIDIA Corporation
4 *
5 * Author: Dipen Patel <dipenp@nvidia.com>
6 */
7
8#include <linux/err.h>

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57#define NV_AON_HTE_SLICE2_IRQ_GPIO_20 20
58#define NV_AON_HTE_SLICE2_IRQ_GPIO_21 21
59#define NV_AON_HTE_SLICE2_IRQ_GPIO_22 22
60#define NV_AON_HTE_SLICE2_IRQ_GPIO_23 23
61#define NV_AON_HTE_SLICE2_IRQ_GPIO_24 24
62#define NV_AON_HTE_SLICE2_IRQ_GPIO_25 25
63#define NV_AON_HTE_SLICE2_IRQ_GPIO_26 26
64#define NV_AON_HTE_SLICE2_IRQ_GPIO_27 27
65#define NV_AON_HTE_SLICE2_IRQ_GPIO_28 28
66#define NV_AON_HTE_SLICE2_IRQ_GPIO_29 29
67#define NV_AON_HTE_SLICE2_IRQ_GPIO_30 30
68#define NV_AON_HTE_SLICE2_IRQ_GPIO_31 31
65
66#define HTE_TECTRL 0x0
67#define HTE_TETSCH 0x4
68#define HTE_TETSCL 0x8
69#define HTE_TESRC 0xC
70#define HTE_TECCV 0x10
71#define HTE_TEPCV 0x14
72#define HTE_TECMD 0x1C

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215 [34] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27},
216 [35] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26},
217 [36] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25},
218 [37] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24},
219 [38] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23},
220 [39] = {NV_AON_SLICE_INVALID, 0},
221};
222
69
70#define HTE_TECTRL 0x0
71#define HTE_TETSCH 0x4
72#define HTE_TETSCL 0x8
73#define HTE_TESRC 0xC
74#define HTE_TECCV 0x10
75#define HTE_TEPCV 0x14
76#define HTE_TECMD 0x1C

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219 [34] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27},
220 [35] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26},
221 [36] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25},
222 [37] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24},
223 [38] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23},
224 [39] = {NV_AON_SLICE_INVALID, 0},
225};
226
223static const struct tegra_hte_data aon_hte = {
227static const struct tegra_hte_line_mapped tegra234_aon_gpio_map[] = {
228 /* gpio, slice, bit_index */
229 /* AA port */
230 [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11},
231 [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10},
232 [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9},
233 [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8},
234 [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7},
235 [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6},
236 [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5},
237 [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4},
238 /* BB port */
239 [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3},
240 [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2},
241 [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1},
242 [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0},
243 /* CC port */
244 [12] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22},
245 [13] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21},
246 [14] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20},
247 [15] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19},
248 [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18},
249 [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17},
250 [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16},
251 [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15},
252 /* DD port */
253 [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14},
254 [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13},
255 [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12},
256 /* EE port */
257 [23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_31},
258 [24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_30},
259 [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_29},
260 [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_28},
261 [27] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27},
262 [28] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26},
263 [29] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25},
264 [30] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24},
265 /* GG port */
266 [31] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23},
267};
268
269static const struct tegra_hte_line_mapped tegra234_aon_gpio_sec_map[] = {
270 /* gpio, slice, bit_index */
271 /* AA port */
272 [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11},
273 [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10},
274 [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9},
275 [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8},
276 [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7},
277 [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6},
278 [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5},
279 [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4},
280 /* BB port */
281 [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3},
282 [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2},
283 [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1},
284 [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0},
285 [12] = {NV_AON_SLICE_INVALID, 0},
286 [13] = {NV_AON_SLICE_INVALID, 0},
287 [14] = {NV_AON_SLICE_INVALID, 0},
288 [15] = {NV_AON_SLICE_INVALID, 0},
289 /* CC port */
290 [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22},
291 [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21},
292 [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20},
293 [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19},
294 [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18},
295 [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17},
296 [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16},
297 [23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15},
298 /* DD port */
299 [24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14},
300 [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13},
301 [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12},
302 [27] = {NV_AON_SLICE_INVALID, 0},
303 [28] = {NV_AON_SLICE_INVALID, 0},
304 [29] = {NV_AON_SLICE_INVALID, 0},
305 [30] = {NV_AON_SLICE_INVALID, 0},
306 [31] = {NV_AON_SLICE_INVALID, 0},
307 /* EE port */
308 [32] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_31},
309 [33] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_30},
310 [34] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_29},
311 [35] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_28},
312 [36] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27},
313 [37] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26},
314 [38] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25},
315 [39] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24},
316 /* GG port */
317 [40] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23},
318};
319
320static const struct tegra_hte_data t194_aon_hte = {
224 .map_sz = ARRAY_SIZE(tegra194_aon_gpio_map),
225 .map = tegra194_aon_gpio_map,
226 .sec_map_sz = ARRAY_SIZE(tegra194_aon_gpio_sec_map),
227 .sec_map = tegra194_aon_gpio_sec_map,
228 .type = HTE_TEGRA_TYPE_GPIO,
229};
230
321 .map_sz = ARRAY_SIZE(tegra194_aon_gpio_map),
322 .map = tegra194_aon_gpio_map,
323 .sec_map_sz = ARRAY_SIZE(tegra194_aon_gpio_sec_map),
324 .sec_map = tegra194_aon_gpio_sec_map,
325 .type = HTE_TEGRA_TYPE_GPIO,
326};
327
328static const struct tegra_hte_data t234_aon_hte = {
329 .map_sz = ARRAY_SIZE(tegra234_aon_gpio_map),
330 .map = tegra234_aon_gpio_map,
331 .sec_map_sz = ARRAY_SIZE(tegra234_aon_gpio_sec_map),
332 .sec_map = tegra234_aon_gpio_sec_map,
333 .type = HTE_TEGRA_TYPE_GPIO,
334};
335
231static const struct tegra_hte_data lic_hte = {
232 .map_sz = 0,
233 .map = NULL,
234 .type = HTE_TEGRA_TYPE_LIC,
235};
236
237static inline u32 tegra_hte_readl(struct tegra_hte_soc *hte, u32 reg)
238{

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530 if (!hte_dev || (hte_dev->prov_data->type != HTE_TEGRA_TYPE_GPIO))
531 return false;
532
533 return hte_dev->c == gpiod_to_chip(hdesc->attr.line_data);
534}
535
536static const struct of_device_id tegra_hte_of_match[] = {
537 { .compatible = "nvidia,tegra194-gte-lic", .data = &lic_hte},
336static const struct tegra_hte_data lic_hte = {
337 .map_sz = 0,
338 .map = NULL,
339 .type = HTE_TEGRA_TYPE_LIC,
340};
341
342static inline u32 tegra_hte_readl(struct tegra_hte_soc *hte, u32 reg)
343{

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635 if (!hte_dev || (hte_dev->prov_data->type != HTE_TEGRA_TYPE_GPIO))
636 return false;
637
638 return hte_dev->c == gpiod_to_chip(hdesc->attr.line_data);
639}
640
641static const struct of_device_id tegra_hte_of_match[] = {
642 { .compatible = "nvidia,tegra194-gte-lic", .data = &lic_hte},
538 { .compatible = "nvidia,tegra194-gte-aon", .data = &aon_hte},
643 { .compatible = "nvidia,tegra194-gte-aon", .data = &t194_aon_hte},
644 { .compatible = "nvidia,tegra234-gte-lic", .data = &lic_hte},
645 { .compatible = "nvidia,tegra234-gte-aon", .data = &t234_aon_hte},
539 { }
540};
541MODULE_DEVICE_TABLE(of, tegra_hte_of_match);
542
543static const struct hte_ops g_ops = {
544 .request = tegra_hte_request,
545 .release = tegra_hte_release,
546 .enable = tegra_hte_enable,

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630 hte_dev->line_data = devm_kcalloc(dev, nlines,
631 sizeof(*hte_dev->line_data),
632 GFP_KERNEL);
633 if (!hte_dev->line_data)
634 return -ENOMEM;
635
636 gc->match_from_linedata = tegra_hte_match_from_linedata;
637
646 { }
647};
648MODULE_DEVICE_TABLE(of, tegra_hte_of_match);
649
650static const struct hte_ops g_ops = {
651 .request = tegra_hte_request,
652 .release = tegra_hte_release,
653 .enable = tegra_hte_enable,

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737 hte_dev->line_data = devm_kcalloc(dev, nlines,
738 sizeof(*hte_dev->line_data),
739 GFP_KERNEL);
740 if (!hte_dev->line_data)
741 return -ENOMEM;
742
743 gc->match_from_linedata = tegra_hte_match_from_linedata;
744
638 hte_dev->c = gpiochip_find("tegra194-gpio-aon",
639 tegra_get_gpiochip_from_name);
745 if (of_device_is_compatible(dev->of_node,
746 "nvidia,tegra194-gte-aon"))
747 hte_dev->c = gpiochip_find("tegra194-gpio-aon",
748 tegra_get_gpiochip_from_name);
749 else if (of_device_is_compatible(dev->of_node,
750 "nvidia,tegra234-gte-aon"))
751 hte_dev->c = gpiochip_find("tegra234-gpio-aon",
752 tegra_get_gpiochip_from_name);
753 else
754 return -ENODEV;
755
640 if (!hte_dev->c)
641 return dev_err_probe(dev, -EPROBE_DEFER,
642 "wait for gpio controller\n");
643 }
644
645 hte_dev->chip = gc;
646
647 ret = devm_hte_register_chip(hte_dev->chip);

--- 83 unchanged lines hidden --- 		756 if (!hte_dev->c)
757 return dev_err_probe(dev, -EPROBE_DEFER,
758 "wait for gpio controller\n");
759 }
760
761 hte_dev->chip = gc;
762
763 ret = devm_hte_register_chip(hte_dev->chip);

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