sor.c (a9a9e4fd7c923707a11b1b386cc31156d474039c) sor.c (4dbdc740c4beec653920e81470a6e6d69c6ab064)
1/*
2 * Copyright (C) 2013 NVIDIA Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8

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1594 sor->dpaux = tegra_dpaux_find_by_of_node(np);
1595 of_node_put(np);
1596
1597 if (!sor->dpaux)
1598 return -EPROBE_DEFER;
1599 }
1600
1601 err = tegra_output_probe(&sor->output);
1/*
2 * Copyright (C) 2013 NVIDIA Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8

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1594 sor->dpaux = tegra_dpaux_find_by_of_node(np);
1595 of_node_put(np);
1596
1597 if (!sor->dpaux)
1598 return -EPROBE_DEFER;
1599 }
1600
1601 err = tegra_output_probe(&sor->output);
1602 if (err < 0)
1602 if (err < 0) {
1603 dev_err(&pdev->dev, "failed to probe output: %d\n", err);
1603 return err;
1604 return err;
1605 }
1604
1605 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1606 sor->regs = devm_ioremap_resource(&pdev->dev, regs);
1607 if (IS_ERR(sor->regs))
1608 return PTR_ERR(sor->regs);
1609
1610 sor->rst = devm_reset_control_get(&pdev->dev, "sor");
1606
1607 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1608 sor->regs = devm_ioremap_resource(&pdev->dev, regs);
1609 if (IS_ERR(sor->regs))
1610 return PTR_ERR(sor->regs);
1611
1612 sor->rst = devm_reset_control_get(&pdev->dev, "sor");
1611 if (IS_ERR(sor->rst))
1613 if (IS_ERR(sor->rst)) {
1614 dev_err(&pdev->dev, "failed to get reset control: %ld\n",
1615 PTR_ERR(sor->rst));
1612 return PTR_ERR(sor->rst);
1616 return PTR_ERR(sor->rst);
1617 }
1613
1614 sor->clk = devm_clk_get(&pdev->dev, NULL);
1618
1619 sor->clk = devm_clk_get(&pdev->dev, NULL);
1615 if (IS_ERR(sor->clk))
1620 if (IS_ERR(sor->clk)) {
1621 dev_err(&pdev->dev, "failed to get module clock: %ld\n",
1622 PTR_ERR(sor->clk));
1616 return PTR_ERR(sor->clk);
1623 return PTR_ERR(sor->clk);
1624 }
1617
1618 sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
1625
1626 sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
1619 if (IS_ERR(sor->clk_parent))
1627 if (IS_ERR(sor->clk_parent)) {
1628 dev_err(&pdev->dev, "failed to get parent clock: %ld\n",
1629 PTR_ERR(sor->clk_parent));
1620 return PTR_ERR(sor->clk_parent);
1630 return PTR_ERR(sor->clk_parent);
1631 }
1621
1622 sor->clk_safe = devm_clk_get(&pdev->dev, "safe");
1632
1633 sor->clk_safe = devm_clk_get(&pdev->dev, "safe");
1623 if (IS_ERR(sor->clk_safe))
1634 if (IS_ERR(sor->clk_safe)) {
1635 dev_err(&pdev->dev, "failed to get safe clock: %ld\n",
1636 PTR_ERR(sor->clk_safe));
1624 return PTR_ERR(sor->clk_safe);
1637 return PTR_ERR(sor->clk_safe);
1638 }
1625
1626 sor->clk_dp = devm_clk_get(&pdev->dev, "dp");
1639
1640 sor->clk_dp = devm_clk_get(&pdev->dev, "dp");
1627 if (IS_ERR(sor->clk_dp))
1641 if (IS_ERR(sor->clk_dp)) {
1642 dev_err(&pdev->dev, "failed to get DP clock: %ld\n",
1643 PTR_ERR(sor->clk_dp));
1628 return PTR_ERR(sor->clk_dp);
1644 return PTR_ERR(sor->clk_dp);
1645 }
1629
1630 INIT_LIST_HEAD(&sor->client.list);
1631 sor->client.ops = &sor_client_ops;
1632 sor->client.dev = &pdev->dev;
1633
1634 mutex_init(&sor->lock);
1635
1636 err = host1x_client_register(&sor->client);

--- 42 unchanged lines hidden --- 		1646
1647 INIT_LIST_HEAD(&sor->client.list);
1648 sor->client.ops = &sor_client_ops;
1649 sor->client.dev = &pdev->dev;
1650
1651 mutex_init(&sor->lock);
1652
1653 err = host1x_client_register(&sor->client);

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