sor.c (9a42c7c647a9ad0f7ebb147a52eda3dcb7c84292) sor.c (f1f20eb9705566f861330f8da7e2f2a84dae46af)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013 NVIDIA Corporation
4 */
5
6#include <linux/clk.h>
7#include <linux/clk-provider.h>
8#include <linux/debugfs.h>

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2156 for (i = length; i < 96; i++)
2157 tegra_sor_writel(sor, i << 8 | 0, SOR_AUDIO_HDA_ELD_BUFWR);
2158}
2159
2160static void tegra_sor_audio_prepare(struct tegra_sor *sor)
2161{
2162 u32 value;
2163
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013 NVIDIA Corporation
4 */
5
6#include <linux/clk.h>
7#include <linux/clk-provider.h>
8#include <linux/debugfs.h>

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2156 for (i = length; i < 96; i++)
2157 tegra_sor_writel(sor, i << 8 | 0, SOR_AUDIO_HDA_ELD_BUFWR);
2158}
2159
2160static void tegra_sor_audio_prepare(struct tegra_sor *sor)
2161{
2162 u32 value;
2163
2164 /*
2165 * Enable and unmask the HDA codec SCRATCH0 register interrupt. This
2166 * is used for interoperability between the HDA codec driver and the
2167 * HDMI/DP driver.
2168 */
2169 value = SOR_INT_CODEC_SCRATCH1 | SOR_INT_CODEC_SCRATCH0;
2170 tegra_sor_writel(sor, value, SOR_INT_ENABLE);
2171 tegra_sor_writel(sor, value, SOR_INT_MASK);
2172
2164 tegra_sor_write_eld(sor);
2165
2166 value = SOR_AUDIO_HDA_PRESENSE_ELDV | SOR_AUDIO_HDA_PRESENSE_PD;
2167 tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE);
2168}
2169
2170static void tegra_sor_audio_unprepare(struct tegra_sor *sor)
2171{
2172 tegra_sor_writel(sor, 0, SOR_AUDIO_HDA_PRESENSE);
2173 tegra_sor_write_eld(sor);
2174
2175 value = SOR_AUDIO_HDA_PRESENSE_ELDV | SOR_AUDIO_HDA_PRESENSE_PD;
2176 tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE);
2177}
2178
2179static void tegra_sor_audio_unprepare(struct tegra_sor *sor)
2180{
2181 tegra_sor_writel(sor, 0, SOR_AUDIO_HDA_PRESENSE);
2182 tegra_sor_writel(sor, 0, SOR_INT_MASK);
2183 tegra_sor_writel(sor, 0, SOR_INT_ENABLE);
2173}
2174
2175static int tegra_sor_hdmi_enable_audio_infoframe(struct tegra_sor *sor)
2176{
2177 u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)];
2178 struct hdmi_audio_infoframe frame;
2179 u32 value;
2180 int err;

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2806
2807static int tegra_sor_init(struct host1x_client *client)
2808{
2809 struct drm_device *drm = dev_get_drvdata(client->parent);
2810 const struct drm_encoder_helper_funcs *helpers = NULL;
2811 struct tegra_sor *sor = host1x_client_to_sor(client);
2812 int connector = DRM_MODE_CONNECTOR_Unknown;
2813 int encoder = DRM_MODE_ENCODER_NONE;
2184}
2185
2186static int tegra_sor_hdmi_enable_audio_infoframe(struct tegra_sor *sor)
2187{
2188 u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)];
2189 struct hdmi_audio_infoframe frame;
2190 u32 value;
2191 int err;

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2817
2818static int tegra_sor_init(struct host1x_client *client)
2819{
2820 struct drm_device *drm = dev_get_drvdata(client->parent);
2821 const struct drm_encoder_helper_funcs *helpers = NULL;
2822 struct tegra_sor *sor = host1x_client_to_sor(client);
2823 int connector = DRM_MODE_CONNECTOR_Unknown;
2824 int encoder = DRM_MODE_ENCODER_NONE;
2814 u32 value;
2815 int err;
2816
2817 if (!sor->aux) {
2818 if (sor->soc->supports_hdmi) {
2819 connector = DRM_MODE_CONNECTOR_HDMIA;
2820 encoder = DRM_MODE_ENCODER_TMDS;
2821 helpers = &tegra_sor_hdmi_helpers;
2822 } else if (sor->soc->supports_lvds) {

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2909 err = clk_prepare_enable(sor->clk_safe);
2910 if (err < 0)
2911 return err;
2912
2913 err = clk_prepare_enable(sor->clk_dp);
2914 if (err < 0)
2915 return err;
2916
2825 int err;
2826
2827 if (!sor->aux) {
2828 if (sor->soc->supports_hdmi) {
2829 connector = DRM_MODE_CONNECTOR_HDMIA;
2830 encoder = DRM_MODE_ENCODER_TMDS;
2831 helpers = &tegra_sor_hdmi_helpers;
2832 } else if (sor->soc->supports_lvds) {

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2919 err = clk_prepare_enable(sor->clk_safe);
2920 if (err < 0)
2921 return err;
2922
2923 err = clk_prepare_enable(sor->clk_dp);
2924 if (err < 0)
2925 return err;
2926
2917 /*
2918 * Enable and unmask the HDA codec SCRATCH0 register interrupt. This
2919 * is used for interoperability between the HDA codec driver and the
2920 * HDMI/DP driver.
2921 */
2922 value = SOR_INT_CODEC_SCRATCH1 | SOR_INT_CODEC_SCRATCH0;
2923 tegra_sor_writel(sor, value, SOR_INT_ENABLE);
2924 tegra_sor_writel(sor, value, SOR_INT_MASK);
2925
2926 return 0;
2927}
2928
2929static int tegra_sor_exit(struct host1x_client *client)
2930{
2931 struct tegra_sor *sor = host1x_client_to_sor(client);
2932 int err;
2933
2927 return 0;
2928}
2929
2930static int tegra_sor_exit(struct host1x_client *client)
2931{
2932 struct tegra_sor *sor = host1x_client_to_sor(client);
2933 int err;
2934
2934 tegra_sor_writel(sor, 0, SOR_INT_MASK);
2935 tegra_sor_writel(sor, 0, SOR_INT_ENABLE);
2936
2937 tegra_output_exit(&sor->output);
2938
2939 if (sor->aux) {
2940 err = drm_dp_aux_detach(sor->aux);
2941 if (err < 0) {
2942 dev_err(sor->dev, "failed to detach DP: %d\n", err);
2943 return err;
2944 }

--- 645 unchanged lines hidden --- 		2935 tegra_output_exit(&sor->output);
2936
2937 if (sor->aux) {
2938 err = drm_dp_aux_detach(sor->aux);
2939 if (err < 0) {
2940 dev_err(sor->dev, "failed to detach DP: %d\n", err);
2941 return err;
2942 }

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