hub.c (1087fac18b8e3ec8fadf1595bbc46dce7ff08a81) hub.c (ab7d3f5826c55ad23101327eab435660caa83436)
1/*
2 * Copyright (C) 2017 NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8

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394 pm_runtime_put(dc->dev);
395}
396
397static void tegra_shared_plane_atomic_update(struct drm_plane *plane,
398 struct drm_plane_state *old_state)
399{
400 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
401 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
1/*
2 * Copyright (C) 2017 NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8

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394 pm_runtime_put(dc->dev);
395}
396
397static void tegra_shared_plane_atomic_update(struct drm_plane *plane,
398 struct drm_plane_state *old_state)
399{
400 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
401 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
402 unsigned int zpos = plane->state->normalized_zpos;
402 struct drm_framebuffer *fb = plane->state->fb;
403 struct tegra_plane *p = to_tegra_plane(plane);
404 struct tegra_bo *bo;
405 dma_addr_t base;
406 u32 value;
407
408 /* rien ne va plus */
409 if (!plane->state->crtc || !plane->state->fb)

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426 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
427 tegra_plane_writel(p, value, DC_WIN_BLEND_MATCH_SELECT);
428
429 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
430 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
431 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
432 tegra_plane_writel(p, value, DC_WIN_BLEND_NOMATCH_SELECT);
433
403 struct drm_framebuffer *fb = plane->state->fb;
404 struct tegra_plane *p = to_tegra_plane(plane);
405 struct tegra_bo *bo;
406 dma_addr_t base;
407 u32 value;
408
409 /* rien ne va plus */
410 if (!plane->state->crtc || !plane->state->fb)

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427 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
428 tegra_plane_writel(p, value, DC_WIN_BLEND_MATCH_SELECT);
429
430 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
431 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
432 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
433 tegra_plane_writel(p, value, DC_WIN_BLEND_NOMATCH_SELECT);
434
434 value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(p->depth);
435 value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - zpos);
435 tegra_plane_writel(p, value, DC_WIN_BLEND_LAYER_CONTROL);
436
437 /* bypass scaling */
438 value = HORIZONTAL_TAPS_5 | VERTICAL_TAPS_5;
439 tegra_plane_writel(p, value, DC_WIN_WINDOWGROUP_SET_CONTROL_INPUT_SCALER);
440
441 value = INPUT_SCALER_VBYPASS | INPUT_SCALER_HBYPASS;
442 tegra_plane_writel(p, value, DC_WIN_WINDOWGROUP_SET_INPUT_SCALER_USAGE);

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531 int err;
532
533 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
534 if (!plane)
535 return ERR_PTR(-ENOMEM);
536
537 plane->base.offset = 0x0a00 + 0x0300 * index;
538 plane->base.index = index;
436 tegra_plane_writel(p, value, DC_WIN_BLEND_LAYER_CONTROL);
437
438 /* bypass scaling */
439 value = HORIZONTAL_TAPS_5 | VERTICAL_TAPS_5;
440 tegra_plane_writel(p, value, DC_WIN_WINDOWGROUP_SET_CONTROL_INPUT_SCALER);
441
442 value = INPUT_SCALER_VBYPASS | INPUT_SCALER_HBYPASS;
443 tegra_plane_writel(p, value, DC_WIN_WINDOWGROUP_SET_INPUT_SCALER_USAGE);

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532 int err;
533
534 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
535 if (!plane)
536 return ERR_PTR(-ENOMEM);
537
538 plane->base.offset = 0x0a00 + 0x0300 * index;
539 plane->base.index = index;
539 plane->base.depth = 0;
540
541 plane->wgrp = &hub->wgrps[wgrp];
542 plane->wgrp->parent = dc->dev;
543
544 p = &plane->base.base;
545
546 num_formats = ARRAY_SIZE(tegra_shared_plane_formats);
547 formats = tegra_shared_plane_formats;
548
549 err = drm_universal_plane_init(drm, p, possible_crtcs,
550 &tegra_plane_funcs, formats,
551 num_formats, NULL, type, NULL);
552 if (err < 0) {
553 kfree(plane);
554 return ERR_PTR(err);
555 }
556
557 drm_plane_helper_add(p, &tegra_shared_plane_helper_funcs);
540
541 plane->wgrp = &hub->wgrps[wgrp];
542 plane->wgrp->parent = dc->dev;
543
544 p = &plane->base.base;
545
546 num_formats = ARRAY_SIZE(tegra_shared_plane_formats);
547 formats = tegra_shared_plane_formats;
548
549 err = drm_universal_plane_init(drm, p, possible_crtcs,
550 &tegra_plane_funcs, formats,
551 num_formats, NULL, type, NULL);
552 if (err < 0) {
553 kfree(plane);
554 return ERR_PTR(err);
555 }
556
557 drm_plane_helper_add(p, &tegra_shared_plane_helper_funcs);
558 drm_plane_create_zpos_property(p, 0, 0, 255);
558
559 return p;
560}
561
562static void tegra_display_hub_update(struct tegra_dc *dc)
563{
564 u32 value;
565

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560 return p;
561}
562
563static void tegra_display_hub_update(struct tegra_dc *dc)
564{
565 u32 value;
566

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