dpaux.c (c728e2d4a6546905f1179a8237860d8d276aaadc) dpaux.c (c176393728c9fcd8f7ef842cb3e4cedda3f418a2)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013 NVIDIA Corporation
4 */
5
6#include <linux/clk.h>
7#include <linux/delay.h>
8#include <linux/gpio.h>

--- 807 unchanged lines hidden (view full) ---

816int drm_dp_aux_disable(struct drm_dp_aux *aux)
817{
818 struct tegra_dpaux *dpaux = to_dpaux(aux);
819
820 tegra_dpaux_pad_power_down(dpaux);
821
822 return 0;
823}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013 NVIDIA Corporation
4 */
5
6#include <linux/clk.h>
7#include <linux/delay.h>
8#include <linux/gpio.h>

--- 807 unchanged lines hidden (view full) ---

816int drm_dp_aux_disable(struct drm_dp_aux *aux)
817{
818 struct tegra_dpaux *dpaux = to_dpaux(aux);
819
820 tegra_dpaux_pad_power_down(dpaux);
821
822 return 0;
823}
824
825int drm_dp_aux_prepare(struct drm_dp_aux *aux, u8 encoding)
826{
827 int err;
828
829 err = drm_dp_dpcd_writeb(aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
830 encoding);
831 if (err < 0)
832 return err;
833
834 return 0;
835}
836
837int drm_dp_aux_train(struct drm_dp_aux *aux, struct drm_dp_link *link,
838 u8 pattern)
839{
840 u8 tp = pattern & DP_TRAINING_PATTERN_MASK;
841 u8 status[DP_LINK_STATUS_SIZE], values[4];
842 unsigned int i;
843 int err;
844
845 err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, pattern);
846 if (err < 0)
847 return err;
848
849 if (tp == DP_TRAINING_PATTERN_DISABLE)
850 return 0;
851
852 for (i = 0; i < link->lanes; i++)
853 values[i] = DP_TRAIN_MAX_PRE_EMPHASIS_REACHED |
854 DP_TRAIN_PRE_EMPH_LEVEL_0 |
855 DP_TRAIN_MAX_SWING_REACHED |
856 DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
857
858 err = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, values,
859 link->lanes);
860 if (err < 0)
861 return err;
862
863 usleep_range(500, 1000);
864
865 err = drm_dp_dpcd_read_link_status(aux, status);
866 if (err < 0)
867 return err;
868
869 switch (tp) {
870 case DP_TRAINING_PATTERN_1:
871 if (!drm_dp_clock_recovery_ok(status, link->lanes))
872 return -EAGAIN;
873
874 break;
875
876 case DP_TRAINING_PATTERN_2:
877 if (!drm_dp_channel_eq_ok(status, link->lanes))
878 return -EAGAIN;
879
880 break;
881
882 default:
883 dev_err(aux->dev, "unsupported training pattern %u\n", tp);
884 return -EINVAL;
885 }
886
887 err = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, 0);
888 if (err < 0)
889 return err;
890
891 return 0;
892}