dc.h (c4755fb9064f64083fe559e92a46df817fc5e07b) dc.h (473079549f27eab5ad449f2c4f079014f0fe74a5)
1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */

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38
39struct tegra_dc_stats {
40 unsigned long frames;
41 unsigned long vblank;
42 unsigned long underflow;
43 unsigned long overflow;
44};
45
1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */

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38
39struct tegra_dc_stats {
40 unsigned long frames;
41 unsigned long vblank;
42 unsigned long underflow;
43 unsigned long overflow;
44};
45
46struct tegra_windowgroup_soc {
47 unsigned int index;
48 unsigned int dc;
49 const unsigned int *windows;
50 unsigned int num_windows;
51};
52
46struct tegra_dc_soc_info {
47 bool supports_background_color;
48 bool supports_interlacing;
49 bool supports_cursor;
50 bool supports_block_linear;
51 unsigned int pitch_align;
52 bool has_powergate;
53 bool broken_reset;
53struct tegra_dc_soc_info {
54 bool supports_background_color;
55 bool supports_interlacing;
56 bool supports_cursor;
57 bool supports_block_linear;
58 unsigned int pitch_align;
59 bool has_powergate;
60 bool broken_reset;
61 bool has_nvdisplay;
62 const struct tegra_windowgroup_soc *wgrps;
63 unsigned int num_wgrps;
54};
55
56struct tegra_dc {
57 struct host1x_client client;
58 struct host1x_syncpt *syncpt;
59 struct device *dev;
60 spinlock_t lock;
61

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175#define PM0_ENABLE (1 << 16)
176#define PM1_ENABLE (1 << 18)
177
178#define DC_CMD_INT_STATUS 0x037
179#define DC_CMD_INT_MASK 0x038
180#define DC_CMD_INT_ENABLE 0x039
181#define DC_CMD_INT_TYPE 0x03a
182#define DC_CMD_INT_POLARITY 0x03b
64};
65
66struct tegra_dc {
67 struct host1x_client client;
68 struct host1x_syncpt *syncpt;
69 struct device *dev;
70 spinlock_t lock;
71

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185#define PM0_ENABLE (1 << 16)
186#define PM1_ENABLE (1 << 18)
187
188#define DC_CMD_INT_STATUS 0x037
189#define DC_CMD_INT_MASK 0x038
190#define DC_CMD_INT_ENABLE 0x039
191#define DC_CMD_INT_TYPE 0x03a
192#define DC_CMD_INT_POLARITY 0x03b
183#define CTXSW_INT (1 << 0)
184#define FRAME_END_INT (1 << 1)
185#define VBLANK_INT (1 << 2)
186#define WIN_A_UF_INT (1 << 8)
187#define WIN_B_UF_INT (1 << 9)
188#define WIN_C_UF_INT (1 << 10)
189#define WIN_A_OF_INT (1 << 14)
190#define WIN_B_OF_INT (1 << 15)
191#define WIN_C_OF_INT (1 << 16)
193#define CTXSW_INT (1 << 0)
194#define FRAME_END_INT (1 << 1)
195#define VBLANK_INT (1 << 2)
196#define V_PULSE3_INT (1 << 4)
197#define V_PULSE2_INT (1 << 5)
198#define REGION_CRC_INT (1 << 6)
199#define REG_TMOUT_INT (1 << 7)
200#define WIN_A_UF_INT (1 << 8)
201#define WIN_B_UF_INT (1 << 9)
202#define WIN_C_UF_INT (1 << 10)
203#define MSF_INT (1 << 12)
204#define WIN_A_OF_INT (1 << 14)
205#define WIN_B_OF_INT (1 << 15)
206#define WIN_C_OF_INT (1 << 16)
207#define HEAD_UF_INT (1 << 23)
208#define SD3_BUCKET_WALK_DONE_INT (1 << 24)
209#define DSC_OBUF_UF_INT (1 << 26)
210#define DSC_RBUF_UF_INT (1 << 27)
211#define DSC_BBUF_UF_INT (1 << 28)
212#define DSC_TO_UF_INT (1 << 29)
192
193#define DC_CMD_SIGNAL_RAISE1 0x03c
194#define DC_CMD_SIGNAL_RAISE2 0x03d
195#define DC_CMD_SIGNAL_RAISE3 0x03e
196
197#define DC_CMD_STATE_ACCESS 0x040
198#define READ_MUX (1 << 0)
199#define WRITE_MUX (1 << 2)

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248#define DC_COM_HSPI_WRITE_DATA_CD 0x323
249#define DC_COM_HSPI_CS_DC 0x324
250#define DC_COM_SCRATCH_REGISTER_A 0x325
251#define DC_COM_SCRATCH_REGISTER_B 0x326
252#define DC_COM_GPIO_CTRL 0x327
253#define DC_COM_GPIO_DEBOUNCE_COUNTER 0x328
254#define DC_COM_CRC_CHECKSUM_LATCHED 0x329
255
213
214#define DC_CMD_SIGNAL_RAISE1 0x03c
215#define DC_CMD_SIGNAL_RAISE2 0x03d
216#define DC_CMD_SIGNAL_RAISE3 0x03e
217
218#define DC_CMD_STATE_ACCESS 0x040
219#define READ_MUX (1 << 0)
220#define WRITE_MUX (1 << 2)

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269#define DC_COM_HSPI_WRITE_DATA_CD 0x323
270#define DC_COM_HSPI_CS_DC 0x324
271#define DC_COM_SCRATCH_REGISTER_A 0x325
272#define DC_COM_SCRATCH_REGISTER_B 0x326
273#define DC_COM_GPIO_CTRL 0x327
274#define DC_COM_GPIO_DEBOUNCE_COUNTER 0x328
275#define DC_COM_CRC_CHECKSUM_LATCHED 0x329
276
277#define DC_COM_RG_UNDERFLOW 0x365
278#define UNDERFLOW_MODE_RED (1 << 8)
279#define UNDERFLOW_REPORT_ENABLE (1 << 0)
280
256#define DC_DISP_DISP_SIGNAL_OPTIONS0 0x400
257#define H_PULSE0_ENABLE (1 << 8)
258#define H_PULSE1_ENABLE (1 << 10)
259#define H_PULSE2_ENABLE (1 << 12)
260
261#define DC_DISP_DISP_SIGNAL_OPTIONS1 0x401
262
263#define DC_DISP_DISP_WIN_OPTIONS 0x402

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370#define DISP_DATA_FORMAT_DF1P3C24B (7 << 0)
371#define DISP_DATA_FORMAT_DF1P3C18B (8 << 0)
372#define DISP_ALIGNMENT_MSB (0 << 8)
373#define DISP_ALIGNMENT_LSB (1 << 8)
374#define DISP_ORDER_RED_BLUE (0 << 9)
375#define DISP_ORDER_BLUE_RED (1 << 9)
376
377#define DC_DISP_DISP_COLOR_CONTROL 0x430
281#define DC_DISP_DISP_SIGNAL_OPTIONS0 0x400
282#define H_PULSE0_ENABLE (1 << 8)
283#define H_PULSE1_ENABLE (1 << 10)
284#define H_PULSE2_ENABLE (1 << 12)
285
286#define DC_DISP_DISP_SIGNAL_OPTIONS1 0x401
287
288#define DC_DISP_DISP_WIN_OPTIONS 0x402

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395#define DISP_DATA_FORMAT_DF1P3C24B (7 << 0)
396#define DISP_DATA_FORMAT_DF1P3C18B (8 << 0)
397#define DISP_ALIGNMENT_MSB (0 << 8)
398#define DISP_ALIGNMENT_LSB (1 << 8)
399#define DISP_ORDER_RED_BLUE (0 << 9)
400#define DISP_ORDER_BLUE_RED (1 << 9)
401
402#define DC_DISP_DISP_COLOR_CONTROL 0x430
378#define BASE_COLOR_SIZE666 (0 << 0)
379#define BASE_COLOR_SIZE111 (1 << 0)
380#define BASE_COLOR_SIZE222 (2 << 0)
381#define BASE_COLOR_SIZE333 (3 << 0)
382#define BASE_COLOR_SIZE444 (4 << 0)
383#define BASE_COLOR_SIZE555 (5 << 0)
384#define BASE_COLOR_SIZE565 (6 << 0)
385#define BASE_COLOR_SIZE332 (7 << 0)
386#define BASE_COLOR_SIZE888 (8 << 0)
403#define BASE_COLOR_SIZE666 ( 0 << 0)
404#define BASE_COLOR_SIZE111 ( 1 << 0)
405#define BASE_COLOR_SIZE222 ( 2 << 0)
406#define BASE_COLOR_SIZE333 ( 3 << 0)
407#define BASE_COLOR_SIZE444 ( 4 << 0)
408#define BASE_COLOR_SIZE555 ( 5 << 0)
409#define BASE_COLOR_SIZE565 ( 6 << 0)
410#define BASE_COLOR_SIZE332 ( 7 << 0)
411#define BASE_COLOR_SIZE888 ( 8 << 0)
412#define BASE_COLOR_SIZE101010 (10 << 0)
413#define BASE_COLOR_SIZE121212 (12 << 0)
387#define DITHER_CONTROL_MASK (3 << 8)
388#define DITHER_CONTROL_DISABLE (0 << 8)
389#define DITHER_CONTROL_ORDERED (2 << 8)
390#define DITHER_CONTROL_ERRDIFF (3 << 8)
391#define BASE_COLOR_SIZE_MASK (0xf << 0)
414#define DITHER_CONTROL_MASK (3 << 8)
415#define DITHER_CONTROL_DISABLE (0 << 8)
416#define DITHER_CONTROL_ORDERED (2 << 8)
417#define DITHER_CONTROL_ERRDIFF (3 << 8)
418#define BASE_COLOR_SIZE_MASK (0xf << 0)
392#define BASE_COLOR_SIZE_666 (0 << 0)
393#define BASE_COLOR_SIZE_111 (1 << 0)
394#define BASE_COLOR_SIZE_222 (2 << 0)
395#define BASE_COLOR_SIZE_333 (3 << 0)
396#define BASE_COLOR_SIZE_444 (4 << 0)
397#define BASE_COLOR_SIZE_555 (5 << 0)
398#define BASE_COLOR_SIZE_565 (6 << 0)
399#define BASE_COLOR_SIZE_332 (7 << 0)
400#define BASE_COLOR_SIZE_888 (8 << 0)
419#define BASE_COLOR_SIZE_666 ( 0 << 0)
420#define BASE_COLOR_SIZE_111 ( 1 << 0)
421#define BASE_COLOR_SIZE_222 ( 2 << 0)
422#define BASE_COLOR_SIZE_333 ( 3 << 0)
423#define BASE_COLOR_SIZE_444 ( 4 << 0)
424#define BASE_COLOR_SIZE_555 ( 5 << 0)
425#define BASE_COLOR_SIZE_565 ( 6 << 0)
426#define BASE_COLOR_SIZE_332 ( 7 << 0)
427#define BASE_COLOR_SIZE_888 ( 8 << 0)
428#define BASE_COLOR_SIZE_101010 ( 10 << 0)
429#define BASE_COLOR_SIZE_121212 ( 12 << 0)
401
402#define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431
403#define SC1_H_QUALIFIER_NONE (1 << 16)
404#define SC0_H_QUALIFIER_NONE (1 << 0)
405
406#define DC_DISP_DATA_ENABLE_OPTIONS 0x432
407#define DE_SELECT_ACTIVE_BLANK (0 << 0)
408#define DE_SELECT_ACTIVE (1 << 0)

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566#define WIN_COLOR_DEPTH_YCbCr422P 20
567#define WIN_COLOR_DEPTH_YUV422P 21
568#define WIN_COLOR_DEPTH_YCbCr422R 22
569#define WIN_COLOR_DEPTH_YUV422R 23
570#define WIN_COLOR_DEPTH_YCbCr422RA 24
571#define WIN_COLOR_DEPTH_YUV422RA 25
572
573#define DC_WIN_POSITION 0x704
430
431#define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431
432#define SC1_H_QUALIFIER_NONE (1 << 16)
433#define SC0_H_QUALIFIER_NONE (1 << 0)
434
435#define DC_DISP_DATA_ENABLE_OPTIONS 0x432
436#define DE_SELECT_ACTIVE_BLANK (0 << 0)
437#define DE_SELECT_ACTIVE (1 << 0)

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595#define WIN_COLOR_DEPTH_YCbCr422P 20
596#define WIN_COLOR_DEPTH_YUV422P 21
597#define WIN_COLOR_DEPTH_YCbCr422R 22
598#define WIN_COLOR_DEPTH_YUV422R 23
599#define WIN_COLOR_DEPTH_YCbCr422RA 24
600#define WIN_COLOR_DEPTH_YUV422RA 25
601
602#define DC_WIN_POSITION 0x704
574#define H_POSITION(x) (((x) & 0x1fff) << 0)
575#define V_POSITION(x) (((x) & 0x1fff) << 16)
603#define H_POSITION(x) (((x) & 0x1fff) << 0) /* XXX 0x7fff on Tegra186 */
604#define V_POSITION(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */
576
577#define DC_WIN_SIZE 0x705
605
606#define DC_WIN_SIZE 0x705
578#define H_SIZE(x) (((x) & 0x1fff) << 0)
579#define V_SIZE(x) (((x) & 0x1fff) << 16)
607#define H_SIZE(x) (((x) & 0x1fff) << 0) /* XXX 0x7fff on Tegra186 */
608#define V_SIZE(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */
580
581#define DC_WIN_PRESCALED_SIZE 0x706
582#define H_PRESCALED_SIZE(x) (((x) & 0x7fff) << 0)
609
610#define DC_WIN_PRESCALED_SIZE 0x706
611#define H_PRESCALED_SIZE(x) (((x) & 0x7fff) << 0)
583#define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16)
612#define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */
584
585#define DC_WIN_H_INITIAL_DDA 0x707
586#define DC_WIN_V_INITIAL_DDA 0x708
587#define DC_WIN_DDA_INC 0x709
588#define H_DDA_INC(x) (((x) & 0xffff) << 0)
589#define V_DDA_INC(x) (((x) & 0xffff) << 16)
590
591#define DC_WIN_LINE_STRIDE 0x70a
592#define DC_WIN_BUF_STRIDE 0x70b
593#define DC_WIN_UV_BUF_STRIDE 0x70c
594#define DC_WIN_BUFFER_ADDR_MODE 0x70d
595#define DC_WIN_BUFFER_ADDR_MODE_LINEAR (0 << 0)
596#define DC_WIN_BUFFER_ADDR_MODE_TILE (1 << 0)
597#define DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV (0 << 16)
598#define DC_WIN_BUFFER_ADDR_MODE_TILE_UV (1 << 16)
613
614#define DC_WIN_H_INITIAL_DDA 0x707
615#define DC_WIN_V_INITIAL_DDA 0x708
616#define DC_WIN_DDA_INC 0x709
617#define H_DDA_INC(x) (((x) & 0xffff) << 0)
618#define V_DDA_INC(x) (((x) & 0xffff) << 16)
619
620#define DC_WIN_LINE_STRIDE 0x70a
621#define DC_WIN_BUF_STRIDE 0x70b
622#define DC_WIN_UV_BUF_STRIDE 0x70c
623#define DC_WIN_BUFFER_ADDR_MODE 0x70d
624#define DC_WIN_BUFFER_ADDR_MODE_LINEAR (0 << 0)
625#define DC_WIN_BUFFER_ADDR_MODE_TILE (1 << 0)
626#define DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV (0 << 16)
627#define DC_WIN_BUFFER_ADDR_MODE_TILE_UV (1 << 16)
628
599#define DC_WIN_DV_CONTROL 0x70e
600
601#define DC_WIN_BLEND_NOKEY 0x70f
602#define DC_WIN_BLEND_1WIN 0x710
603#define DC_WIN_BLEND_2WIN_X 0x711
604#define DC_WIN_BLEND_2WIN_Y 0x712
605#define DC_WIN_BLEND_3WIN_XY 0x713
606

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630#define DC_WINBUF_CDE_CONTROL 0x82f
631#define ENABLE_SURFACE (1 << 0)
632
633#define DC_WINBUF_AD_UFLOW_STATUS 0xbca
634#define DC_WINBUF_BD_UFLOW_STATUS 0xdca
635#define DC_WINBUF_CD_UFLOW_STATUS 0xfca
636
637/* Tegra186 and later */
629#define DC_WIN_DV_CONTROL 0x70e
630
631#define DC_WIN_BLEND_NOKEY 0x70f
632#define DC_WIN_BLEND_1WIN 0x710
633#define DC_WIN_BLEND_2WIN_X 0x711
634#define DC_WIN_BLEND_2WIN_Y 0x712
635#define DC_WIN_BLEND_3WIN_XY 0x713
636

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660#define DC_WINBUF_CDE_CONTROL 0x82f
661#define ENABLE_SURFACE (1 << 0)
662
663#define DC_WINBUF_AD_UFLOW_STATUS 0xbca
664#define DC_WINBUF_BD_UFLOW_STATUS 0xdca
665#define DC_WINBUF_CD_UFLOW_STATUS 0xfca
666
667/* Tegra186 and later */
668#define DC_DISP_CORE_SOR_SET_CONTROL(x) (0x403 + (x))
669#define PROTOCOL_MASK (0xf << 8)
670#define PROTOCOL_SINGLE_TMDS_A (0x1 << 8)
671
638#define DC_WIN_CORE_WINDOWGROUP_SET_CONTROL 0x702
639#define OWNER_MASK (0xf << 0)
640#define OWNER(x) (((x) & 0xf) << 0)
641
642#define DC_WIN_CROPPED_SIZE 0x706
643
644#define DC_WIN_PLANAR_STORAGE 0x709
645#define PITCH(x) (((x) >> 6) & 0x1fff)

--- 72 unchanged lines hidden --- 		672#define DC_WIN_CORE_WINDOWGROUP_SET_CONTROL 0x702
673#define OWNER_MASK (0xf << 0)
674#define OWNER(x) (((x) & 0xf) << 0)
675
676#define DC_WIN_CROPPED_SIZE 0x706
677
678#define DC_WIN_PLANAR_STORAGE 0x709
679#define PITCH(x) (((x) >> 6) & 0x1fff)

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