dc.c (363541e8eeed16fdf696252008ddee823730f82c) | dc.c (ab7d3f5826c55ad23101327eab435660caa83436) |
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1/* 2 * Copyright (C) 2012 Avionic Design GmbH 3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 */ --- 138 unchanged lines hidden (view full) --- 147} 148 149static inline u32 compute_initial_dda(unsigned int in) 150{ 151 fixed20_12 inf = dfixed_init(in); 152 return dfixed_frac(inf); 153} 154 | 1/* 2 * Copyright (C) 2012 Avionic Design GmbH 3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 */ --- 138 unchanged lines hidden (view full) --- 147} 148 149static inline u32 compute_initial_dda(unsigned int in) 150{ 151 fixed20_12 inf = dfixed_init(in); 152 return dfixed_frac(inf); 153} 154 |
155static void tegra_plane_setup_blending_legacy(struct tegra_plane *plane) 156{ 157 /* 158 * Disable blending and assume Window A is the bottom-most window, 159 * Window C is the top-most window and Window B is in the middle. 160 */ 161 tegra_plane_writel(plane, 0xffff00, DC_WIN_BLEND_NOKEY); 162 tegra_plane_writel(plane, 0xffff00, DC_WIN_BLEND_1WIN); 163 164 switch (plane->index) { 165 case 0: 166 tegra_plane_writel(plane, 0x000000, DC_WIN_BLEND_2WIN_X); 167 tegra_plane_writel(plane, 0x000000, DC_WIN_BLEND_2WIN_Y); 168 tegra_plane_writel(plane, 0x000000, DC_WIN_BLEND_3WIN_XY); 169 break; 170 171 case 1: 172 tegra_plane_writel(plane, 0xffff00, DC_WIN_BLEND_2WIN_X); 173 tegra_plane_writel(plane, 0x000000, DC_WIN_BLEND_2WIN_Y); 174 tegra_plane_writel(plane, 0x000000, DC_WIN_BLEND_3WIN_XY); 175 break; 176 177 case 2: 178 tegra_plane_writel(plane, 0xffff00, DC_WIN_BLEND_2WIN_X); 179 tegra_plane_writel(plane, 0xffff00, DC_WIN_BLEND_2WIN_Y); 180 tegra_plane_writel(plane, 0xffff00, DC_WIN_BLEND_3WIN_XY); 181 break; 182 } 183} 184 185static void tegra_plane_setup_blending(struct tegra_plane *plane, 186 const struct tegra_dc_window *window) 187{ 188 u32 value; 189 190 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 | 191 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC | 192 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC; 193 tegra_plane_writel(plane, value, DC_WIN_BLEND_MATCH_SELECT); 194 195 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 | 196 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC | 197 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC; 198 tegra_plane_writel(plane, value, DC_WIN_BLEND_NOMATCH_SELECT); 199 200 value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - window->zpos); 201 tegra_plane_writel(plane, value, DC_WIN_BLEND_LAYER_CONTROL); 202} 203 |
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155static void tegra_dc_setup_window(struct tegra_plane *plane, 156 const struct tegra_dc_window *window) 157{ 158 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp; 159 struct tegra_dc *dc = plane->dc; 160 bool yuv, planar; 161 u32 value; 162 --- 123 unchanged lines hidden (view full) --- 286 value |= COLOR_EXPAND; 287 } 288 289 if (window->bottom_up) 290 value |= V_DIRECTION; 291 292 tegra_plane_writel(plane, value, DC_WIN_WIN_OPTIONS); 293 | 204static void tegra_dc_setup_window(struct tegra_plane *plane, 205 const struct tegra_dc_window *window) 206{ 207 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp; 208 struct tegra_dc *dc = plane->dc; 209 bool yuv, planar; 210 u32 value; 211 --- 123 unchanged lines hidden (view full) --- 335 value |= COLOR_EXPAND; 336 } 337 338 if (window->bottom_up) 339 value |= V_DIRECTION; 340 341 tegra_plane_writel(plane, value, DC_WIN_WIN_OPTIONS); 342 |
294 /* 295 * Disable blending and assume Window A is the bottom-most window, 296 * Window C is the top-most window and Window B is in the middle. 297 */ 298 tegra_plane_writel(plane, 0xffff00, DC_WIN_BLEND_NOKEY); 299 tegra_plane_writel(plane, 0xffff00, DC_WIN_BLEND_1WIN); 300 301 switch (plane->index) { 302 case 0: 303 tegra_plane_writel(plane, 0x000000, DC_WIN_BLEND_2WIN_X); 304 tegra_plane_writel(plane, 0x000000, DC_WIN_BLEND_2WIN_Y); 305 tegra_plane_writel(plane, 0x000000, DC_WIN_BLEND_3WIN_XY); 306 break; 307 308 case 1: 309 tegra_plane_writel(plane, 0xffff00, DC_WIN_BLEND_2WIN_X); 310 tegra_plane_writel(plane, 0x000000, DC_WIN_BLEND_2WIN_Y); 311 tegra_plane_writel(plane, 0x000000, DC_WIN_BLEND_3WIN_XY); 312 break; 313 314 case 2: 315 tegra_plane_writel(plane, 0xffff00, DC_WIN_BLEND_2WIN_X); 316 tegra_plane_writel(plane, 0xffff00, DC_WIN_BLEND_2WIN_Y); 317 tegra_plane_writel(plane, 0xffff00, DC_WIN_BLEND_3WIN_XY); 318 break; 319 } | 343 if (dc->soc->supports_blending) 344 tegra_plane_setup_blending(plane, window); 345 else 346 tegra_plane_setup_blending_legacy(plane); |
320} 321 322static const u32 tegra20_primary_formats[] = { 323 DRM_FORMAT_ARGB4444, 324 DRM_FORMAT_ARGB1555, 325 DRM_FORMAT_RGB565, 326 DRM_FORMAT_RGBA5551, 327 DRM_FORMAT_ABGR8888, --- 134 unchanged lines hidden (view full) --- 462 window.dst.x = plane->state->dst.x1; 463 window.dst.y = plane->state->dst.y1; 464 window.dst.w = drm_rect_width(&plane->state->dst); 465 window.dst.h = drm_rect_height(&plane->state->dst); 466 window.bits_per_pixel = fb->format->cpp[0] * 8; 467 window.bottom_up = tegra_fb_is_bottom_up(fb); 468 469 /* copy from state */ | 347} 348 349static const u32 tegra20_primary_formats[] = { 350 DRM_FORMAT_ARGB4444, 351 DRM_FORMAT_ARGB1555, 352 DRM_FORMAT_RGB565, 353 DRM_FORMAT_RGBA5551, 354 DRM_FORMAT_ABGR8888, --- 134 unchanged lines hidden (view full) --- 489 window.dst.x = plane->state->dst.x1; 490 window.dst.y = plane->state->dst.y1; 491 window.dst.w = drm_rect_width(&plane->state->dst); 492 window.dst.h = drm_rect_height(&plane->state->dst); 493 window.bits_per_pixel = fb->format->cpp[0] * 8; 494 window.bottom_up = tegra_fb_is_bottom_up(fb); 495 496 /* copy from state */ |
497 window.zpos = plane->state->normalized_zpos; |
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470 window.tiling = state->tiling; 471 window.format = state->format; 472 window.swap = state->swap; 473 474 for (i = 0; i < fb->format->num_planes; i++) { 475 struct tegra_bo *bo = tegra_fb_get_plane(fb, i); 476 477 window.base[i] = bo->paddr + fb->offsets[i]; --- 40 unchanged lines hidden (view full) --- 518 519 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 520 if (!plane) 521 return ERR_PTR(-ENOMEM); 522 523 /* Always use window A as primary window */ 524 plane->offset = 0xa00; 525 plane->index = 0; | 498 window.tiling = state->tiling; 499 window.format = state->format; 500 window.swap = state->swap; 501 502 for (i = 0; i < fb->format->num_planes; i++) { 503 struct tegra_bo *bo = tegra_fb_get_plane(fb, i); 504 505 window.base[i] = bo->paddr + fb->offsets[i]; --- 40 unchanged lines hidden (view full) --- 546 547 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 548 if (!plane) 549 return ERR_PTR(-ENOMEM); 550 551 /* Always use window A as primary window */ 552 plane->offset = 0xa00; 553 plane->index = 0; |
526 plane->depth = 255; | |
527 plane->dc = dc; 528 529 num_formats = dc->soc->num_primary_formats; 530 formats = dc->soc->primary_formats; 531 532 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, 533 &tegra_plane_funcs, formats, 534 num_formats, NULL, type, NULL); 535 if (err < 0) { 536 kfree(plane); 537 return ERR_PTR(err); 538 } 539 540 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs); 541 | 554 plane->dc = dc; 555 556 num_formats = dc->soc->num_primary_formats; 557 formats = dc->soc->primary_formats; 558 559 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, 560 &tegra_plane_funcs, formats, 561 num_formats, NULL, type, NULL); 562 if (err < 0) { 563 kfree(plane); 564 return ERR_PTR(err); 565 } 566 567 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs); 568 |
569 if (dc->soc->supports_blending) 570 drm_plane_create_zpos_property(&plane->base, 0, 0, 255); 571 |
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542 return &plane->base; 543} 544 545static const u32 tegra_cursor_plane_formats[] = { 546 DRM_FORMAT_RGBA8888, 547}; 548 549static int tegra_cursor_atomic_check(struct drm_plane *plane, --- 231 unchanged lines hidden (view full) --- 781 int err; 782 783 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 784 if (!plane) 785 return ERR_PTR(-ENOMEM); 786 787 plane->offset = 0xa00 + 0x200 * index; 788 plane->index = index; | 572 return &plane->base; 573} 574 575static const u32 tegra_cursor_plane_formats[] = { 576 DRM_FORMAT_RGBA8888, 577}; 578 579static int tegra_cursor_atomic_check(struct drm_plane *plane, --- 231 unchanged lines hidden (view full) --- 811 int err; 812 813 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 814 if (!plane) 815 return ERR_PTR(-ENOMEM); 816 817 plane->offset = 0xa00 + 0x200 * index; 818 plane->index = index; |
789 plane->depth = 0; | |
790 plane->dc = dc; 791 792 num_formats = dc->soc->num_overlay_formats; 793 formats = dc->soc->overlay_formats; 794 795 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe, 796 &tegra_plane_funcs, formats, 797 num_formats, NULL, 798 DRM_PLANE_TYPE_OVERLAY, NULL); 799 if (err < 0) { 800 kfree(plane); 801 return ERR_PTR(err); 802 } 803 804 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs); 805 | 819 plane->dc = dc; 820 821 num_formats = dc->soc->num_overlay_formats; 822 formats = dc->soc->overlay_formats; 823 824 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe, 825 &tegra_plane_funcs, formats, 826 num_formats, NULL, 827 DRM_PLANE_TYPE_OVERLAY, NULL); 828 if (err < 0) { 829 kfree(plane); 830 return ERR_PTR(err); 831 } 832 833 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs); 834 |
835 if (dc->soc->supports_blending) 836 drm_plane_create_zpos_property(&plane->base, 0, 0, 255); 837 |
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806 return &plane->base; 807} 808 809static struct drm_plane *tegra_dc_add_shared_planes(struct drm_device *drm, 810 struct tegra_dc *dc) 811{ 812 struct drm_plane *plane, *primary = NULL; 813 unsigned int i, j; --- 1015 unchanged lines hidden (view full) --- 1829 .exit = tegra_dc_exit, 1830}; 1831 1832static const struct tegra_dc_soc_info tegra20_dc_soc_info = { 1833 .supports_background_color = false, 1834 .supports_interlacing = false, 1835 .supports_cursor = false, 1836 .supports_block_linear = false, | 838 return &plane->base; 839} 840 841static struct drm_plane *tegra_dc_add_shared_planes(struct drm_device *drm, 842 struct tegra_dc *dc) 843{ 844 struct drm_plane *plane, *primary = NULL; 845 unsigned int i, j; --- 1015 unchanged lines hidden (view full) --- 1861 .exit = tegra_dc_exit, 1862}; 1863 1864static const struct tegra_dc_soc_info tegra20_dc_soc_info = { 1865 .supports_background_color = false, 1866 .supports_interlacing = false, 1867 .supports_cursor = false, 1868 .supports_block_linear = false, |
1869 .supports_blending = false, |
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1837 .pitch_align = 8, 1838 .has_powergate = false, 1839 .broken_reset = true, 1840 .has_nvdisplay = false, 1841 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats), 1842 .primary_formats = tegra20_primary_formats, 1843 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats), 1844 .overlay_formats = tegra20_overlay_formats, 1845}; 1846 1847static const struct tegra_dc_soc_info tegra30_dc_soc_info = { 1848 .supports_background_color = false, 1849 .supports_interlacing = false, 1850 .supports_cursor = false, 1851 .supports_block_linear = false, | 1870 .pitch_align = 8, 1871 .has_powergate = false, 1872 .broken_reset = true, 1873 .has_nvdisplay = false, 1874 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats), 1875 .primary_formats = tegra20_primary_formats, 1876 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats), 1877 .overlay_formats = tegra20_overlay_formats, 1878}; 1879 1880static const struct tegra_dc_soc_info tegra30_dc_soc_info = { 1881 .supports_background_color = false, 1882 .supports_interlacing = false, 1883 .supports_cursor = false, 1884 .supports_block_linear = false, |
1885 .supports_blending = false, |
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1852 .pitch_align = 8, 1853 .has_powergate = false, 1854 .broken_reset = false, 1855 .has_nvdisplay = false, 1856 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats), 1857 .primary_formats = tegra20_primary_formats, 1858 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats), 1859 .overlay_formats = tegra20_overlay_formats, 1860}; 1861 1862static const struct tegra_dc_soc_info tegra114_dc_soc_info = { 1863 .supports_background_color = false, 1864 .supports_interlacing = false, 1865 .supports_cursor = false, 1866 .supports_block_linear = false, | 1886 .pitch_align = 8, 1887 .has_powergate = false, 1888 .broken_reset = false, 1889 .has_nvdisplay = false, 1890 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats), 1891 .primary_formats = tegra20_primary_formats, 1892 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats), 1893 .overlay_formats = tegra20_overlay_formats, 1894}; 1895 1896static const struct tegra_dc_soc_info tegra114_dc_soc_info = { 1897 .supports_background_color = false, 1898 .supports_interlacing = false, 1899 .supports_cursor = false, 1900 .supports_block_linear = false, |
1901 .supports_blending = false, |
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1867 .pitch_align = 64, 1868 .has_powergate = true, 1869 .broken_reset = false, 1870 .has_nvdisplay = false, 1871 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats), 1872 .primary_formats = tegra114_primary_formats, 1873 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats), 1874 .overlay_formats = tegra114_overlay_formats, 1875}; 1876 1877static const struct tegra_dc_soc_info tegra124_dc_soc_info = { 1878 .supports_background_color = true, 1879 .supports_interlacing = true, 1880 .supports_cursor = true, 1881 .supports_block_linear = true, | 1902 .pitch_align = 64, 1903 .has_powergate = true, 1904 .broken_reset = false, 1905 .has_nvdisplay = false, 1906 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats), 1907 .primary_formats = tegra114_primary_formats, 1908 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats), 1909 .overlay_formats = tegra114_overlay_formats, 1910}; 1911 1912static const struct tegra_dc_soc_info tegra124_dc_soc_info = { 1913 .supports_background_color = true, 1914 .supports_interlacing = true, 1915 .supports_cursor = true, 1916 .supports_block_linear = true, |
1917 .supports_blending = true, |
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1882 .pitch_align = 64, 1883 .has_powergate = true, 1884 .broken_reset = false, 1885 .has_nvdisplay = false, 1886 .num_primary_formats = ARRAY_SIZE(tegra124_primary_formats), 1887 .primary_formats = tegra114_primary_formats, 1888 .num_overlay_formats = ARRAY_SIZE(tegra124_overlay_formats), 1889 .overlay_formats = tegra114_overlay_formats, 1890}; 1891 1892static const struct tegra_dc_soc_info tegra210_dc_soc_info = { 1893 .supports_background_color = true, 1894 .supports_interlacing = true, 1895 .supports_cursor = true, 1896 .supports_block_linear = true, | 1918 .pitch_align = 64, 1919 .has_powergate = true, 1920 .broken_reset = false, 1921 .has_nvdisplay = false, 1922 .num_primary_formats = ARRAY_SIZE(tegra124_primary_formats), 1923 .primary_formats = tegra114_primary_formats, 1924 .num_overlay_formats = ARRAY_SIZE(tegra124_overlay_formats), 1925 .overlay_formats = tegra114_overlay_formats, 1926}; 1927 1928static const struct tegra_dc_soc_info tegra210_dc_soc_info = { 1929 .supports_background_color = true, 1930 .supports_interlacing = true, 1931 .supports_cursor = true, 1932 .supports_block_linear = true, |
1933 .supports_blending = true, |
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1897 .pitch_align = 64, 1898 .has_powergate = true, 1899 .broken_reset = false, 1900 .has_nvdisplay = false, 1901 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats), 1902 .primary_formats = tegra114_primary_formats, 1903 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats), 1904 .overlay_formats = tegra114_overlay_formats, --- 33 unchanged lines hidden (view full) --- 1938 }, 1939}; 1940 1941static const struct tegra_dc_soc_info tegra186_dc_soc_info = { 1942 .supports_background_color = true, 1943 .supports_interlacing = true, 1944 .supports_cursor = true, 1945 .supports_block_linear = true, | 1934 .pitch_align = 64, 1935 .has_powergate = true, 1936 .broken_reset = false, 1937 .has_nvdisplay = false, 1938 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats), 1939 .primary_formats = tegra114_primary_formats, 1940 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats), 1941 .overlay_formats = tegra114_overlay_formats, --- 33 unchanged lines hidden (view full) --- 1975 }, 1976}; 1977 1978static const struct tegra_dc_soc_info tegra186_dc_soc_info = { 1979 .supports_background_color = true, 1980 .supports_interlacing = true, 1981 .supports_cursor = true, 1982 .supports_block_linear = true, |
1983 .supports_blending = true, |
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1946 .pitch_align = 64, 1947 .has_powergate = false, 1948 .broken_reset = false, 1949 .has_nvdisplay = true, 1950 .wgrps = tegra186_dc_wgrps, 1951 .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps), 1952}; 1953 --- 244 unchanged lines hidden --- | 1984 .pitch_align = 64, 1985 .has_powergate = false, 1986 .broken_reset = false, 1987 .has_nvdisplay = true, 1988 .wgrps = tegra186_dc_wgrps, 1989 .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps), 1990}; 1991 --- 244 unchanged lines hidden --- |