si.c (ba4b60e85d6c5fc2242fd24e131a47fb922e5d89) si.c (ff212f25feb44a915ce9c0144faef7fae27a6e61)
1/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

--- 3420 unchanged lines hidden (view full) ---

3429 WREG32(SCRATCH_UMSK, 0);
3430 }
3431
3432 mdelay(1);
3433 WREG32(CP_RB0_CNTL, tmp);
3434
3435 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
3436
1/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

--- 3420 unchanged lines hidden (view full) ---

3429 WREG32(SCRATCH_UMSK, 0);
3430 }
3431
3432 mdelay(1);
3433 WREG32(CP_RB0_CNTL, tmp);
3434
3435 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
3436
3437 ring->rptr = RREG32(CP_RB0_RPTR);
3438
3439 /* ring1 - compute only */
3440 /* Set ring buffer size */
3441 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
3442 rb_bufsz = order_base_2(ring->ring_size / 8);
3443 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3444#ifdef __BIG_ENDIAN
3445 tmp |= BUF_SWAP_32BIT;
3446#endif

--- 8 unchanged lines hidden (view full) ---

3455 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
3456 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
3457
3458 mdelay(1);
3459 WREG32(CP_RB1_CNTL, tmp);
3460
3461 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
3462
3437 /* ring1 - compute only */
3438 /* Set ring buffer size */
3439 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
3440 rb_bufsz = order_base_2(ring->ring_size / 8);
3441 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3442#ifdef __BIG_ENDIAN
3443 tmp |= BUF_SWAP_32BIT;
3444#endif

--- 8 unchanged lines hidden (view full) ---

3453 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
3454 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
3455
3456 mdelay(1);
3457 WREG32(CP_RB1_CNTL, tmp);
3458
3459 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
3460
3463 ring->rptr = RREG32(CP_RB1_RPTR);
3464
3465 /* ring2 - compute only */
3466 /* Set ring buffer size */
3467 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
3468 rb_bufsz = order_base_2(ring->ring_size / 8);
3469 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3470#ifdef __BIG_ENDIAN
3471 tmp |= BUF_SWAP_32BIT;
3472#endif

--- 8 unchanged lines hidden (view full) ---

3481 WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
3482 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
3483
3484 mdelay(1);
3485 WREG32(CP_RB2_CNTL, tmp);
3486
3487 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
3488
3461 /* ring2 - compute only */
3462 /* Set ring buffer size */
3463 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
3464 rb_bufsz = order_base_2(ring->ring_size / 8);
3465 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3466#ifdef __BIG_ENDIAN
3467 tmp |= BUF_SWAP_32BIT;
3468#endif

--- 8 unchanged lines hidden (view full) ---

3477 WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
3478 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
3479
3480 mdelay(1);
3481 WREG32(CP_RB2_CNTL, tmp);
3482
3483 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
3484
3489 ring->rptr = RREG32(CP_RB2_RPTR);
3490
3491 /* start the rings */
3492 si_cp_start(rdev);
3493 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
3494 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = true;
3495 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = true;
3496 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
3497 if (r) {
3498 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;

--- 368 unchanged lines hidden (view full) ---

3867 */
3868bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
3869{
3870 u32 reset_mask = si_gpu_check_soft_reset(rdev);
3871
3872 if (!(reset_mask & (RADEON_RESET_GFX |
3873 RADEON_RESET_COMPUTE |
3874 RADEON_RESET_CP))) {
3485 /* start the rings */
3486 si_cp_start(rdev);
3487 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
3488 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = true;
3489 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = true;
3490 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
3491 if (r) {
3492 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;

--- 368 unchanged lines hidden (view full) ---

3861 */
3862bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
3863{
3864 u32 reset_mask = si_gpu_check_soft_reset(rdev);
3865
3866 if (!(reset_mask & (RADEON_RESET_GFX |
3867 RADEON_RESET_COMPUTE |
3868 RADEON_RESET_CP))) {
3875 radeon_ring_lockup_update(ring);
3869 radeon_ring_lockup_update(rdev, ring);
3876 return false;
3877 }
3878 /* force CP activities */
3879 radeon_ring_force_activity(rdev, ring);
3880 return radeon_ring_test_lockup(rdev, ring);
3881}
3882
3883/* MC */

--- 3401 unchanged lines hidden --- 		3870 return false;
3871 }
3872 /* force CP activities */
3873 radeon_ring_force_activity(rdev, ring);
3874 return radeon_ring_test_lockup(rdev, ring);
3875}
3876
3877/* MC */

--- 3401 unchanged lines hidden ---