si.c (6ba81e538a786281a9650efd14c6a194f35bde04) si.c (24c164393dd2fa1c1fb51d5fec2f50bd6b7c037b)
1/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

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73extern int r600_ih_ring_alloc(struct radeon_device *rdev);
74extern void r600_ih_ring_fini(struct radeon_device *rdev);
75extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
76extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
77extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
78extern u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev);
79extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
80extern bool evergreen_is_display_hung(struct radeon_device *rdev);
1/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

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73extern int r600_ih_ring_alloc(struct radeon_device *rdev);
74extern void r600_ih_ring_fini(struct radeon_device *rdev);
75extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
76extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
77extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
78extern u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev);
79extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
80extern bool evergreen_is_display_hung(struct radeon_device *rdev);
81extern void si_dma_vm_set_page(struct radeon_device *rdev,
82 struct radeon_ib *ib,
83 uint64_t pe,
84 uint64_t addr, unsigned count,
85 uint32_t incr, uint32_t flags);
86static void si_enable_gui_idle_interrupt(struct radeon_device *rdev,
87 bool enable);
88
89static const u32 verde_rlc_save_restore_register_list[] =
90{
91 (0x8000 << 16) | (0x98f4 >> 2),
92 0x00000000,
93 (0x8040 << 16) | (0x98f4 >> 2),

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4657 }
4658
4659 printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n",
4660 protections, vmid, addr,
4661 (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read",
4662 block, mc_id);
4663}
4664
81static void si_enable_gui_idle_interrupt(struct radeon_device *rdev,
82 bool enable);
83
84static const u32 verde_rlc_save_restore_register_list[] =
85{
86 (0x8000 << 16) | (0x98f4 >> 2),
87 0x00000000,
88 (0x8040 << 16) | (0x98f4 >> 2),

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4652 }
4653
4654 printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n",
4655 protections, vmid, addr,
4656 (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read",
4657 block, mc_id);
4658}
4659
4665/**
4666 * si_vm_set_page - update the page tables using the CP
4667 *
4668 * @rdev: radeon_device pointer
4669 * @ib: indirect buffer to fill with commands
4670 * @pe: addr of the page entry
4671 * @addr: dst addr to write into pe
4672 * @count: number of page entries to update
4673 * @incr: increase next addr by incr bytes
4674 * @flags: access flags
4675 *
4676 * Update the page tables using the CP (SI).
4677 */
4678void si_vm_set_page(struct radeon_device *rdev,
4679 struct radeon_ib *ib,
4680 uint64_t pe,
4681 uint64_t addr, unsigned count,
4682 uint32_t incr, uint32_t flags)
4683{
4684 uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
4685 uint64_t value;
4686 unsigned ndw;
4687
4688 if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) {
4689 while (count) {
4690 ndw = 2 + count * 2;
4691 if (ndw > 0x3FFE)
4692 ndw = 0x3FFE;
4693
4694 ib->ptr[ib->length_dw++] = PACKET3(PACKET3_WRITE_DATA, ndw);
4695 ib->ptr[ib->length_dw++] = (WRITE_DATA_ENGINE_SEL(0) |
4696 WRITE_DATA_DST_SEL(1));
4697 ib->ptr[ib->length_dw++] = pe;
4698 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
4699 for (; ndw > 2; ndw -= 2, --count, pe += 8) {
4700 if (flags & RADEON_VM_PAGE_SYSTEM) {
4701 value = radeon_vm_map_gart(rdev, addr);
4702 value &= 0xFFFFFFFFFFFFF000ULL;
4703 } else if (flags & RADEON_VM_PAGE_VALID) {
4704 value = addr;
4705 } else {
4706 value = 0;
4707 }
4708 addr += incr;
4709 value |= r600_flags;
4710 ib->ptr[ib->length_dw++] = value;
4711 ib->ptr[ib->length_dw++] = upper_32_bits(value);
4712 }
4713 }
4714 } else {
4715 /* DMA */
4716 si_dma_vm_set_page(rdev, ib, pe, addr, count, incr, flags);
4717 }
4718}
4719
4720void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
4721{
4722 struct radeon_ring *ring = &rdev->ring[ridx];
4723
4724 if (vm == NULL)
4725 return;
4726
4727 /* write new base address */

--- 2476 unchanged lines hidden --- 		4660void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
4661{
4662 struct radeon_ring *ring = &rdev->ring[ridx];
4663
4664 if (vm == NULL)
4665 return;
4666
4667 /* write new base address */

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