rv770.c (1614f8b17b8cc3ad143541d41569623d30dbc9ec) rv770.c (4c7886791264f03428d5424befb1b96f08fc90f4)
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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87 r600_pcie_gart_tlb_flush(rdev);
88 rdev->gart.ready = true;
89 return 0;
90}
91
92void rv770_pcie_gart_disable(struct radeon_device *rdev)
93{
94 u32 tmp;
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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87 r600_pcie_gart_tlb_flush(rdev);
88 rdev->gart.ready = true;
89 return 0;
90}
91
92void rv770_pcie_gart_disable(struct radeon_device *rdev)
93{
94 u32 tmp;
95 int i;
95 int i, r;
96
97 /* Disable all tables */
98 for (i = 0; i < 7; i++)
99 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
100
101 /* Setup L2 cache */
102 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
103 EFFECTIVE_L2_QUEUE_SIZE(7));

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108 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
109 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
110 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
111 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
112 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
113 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
114 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
115 if (rdev->gart.table.vram.robj) {
96
97 /* Disable all tables */
98 for (i = 0; i < 7; i++)
99 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
100
101 /* Setup L2 cache */
102 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
103 EFFECTIVE_L2_QUEUE_SIZE(7));

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108 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
109 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
110 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
111 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
112 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
113 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
114 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
115 if (rdev->gart.table.vram.robj) {
116 radeon_object_kunmap(rdev->gart.table.vram.robj);
117 radeon_object_unpin(rdev->gart.table.vram.robj);
116 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
117 if (likely(r == 0)) {
118 radeon_bo_kunmap(rdev->gart.table.vram.robj);
119 radeon_bo_unpin(rdev->gart.table.vram.robj);
120 radeon_bo_unreserve(rdev->gart.table.vram.robj);
121 }
118 }
119}
120
121void rv770_pcie_gart_fini(struct radeon_device *rdev)
122{
123 rv770_pcie_gart_disable(rdev);
124 radeon_gart_table_vram_free(rdev);
125 radeon_gart_fini(rdev);

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875 rv770_agp_enable(rdev);
876 } else {
877 r = rv770_pcie_gart_enable(rdev);
878 if (r)
879 return r;
880 }
881 rv770_gpu_init(rdev);
882
122 }
123}
124
125void rv770_pcie_gart_fini(struct radeon_device *rdev)
126{
127 rv770_pcie_gart_disable(rdev);
128 radeon_gart_table_vram_free(rdev);
129 radeon_gart_fini(rdev);

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879 rv770_agp_enable(rdev);
880 } else {
881 r = rv770_pcie_gart_enable(rdev);
882 if (r)
883 return r;
884 }
885 rv770_gpu_init(rdev);
886
883 r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
884 &rdev->r600_blit.shader_gpu_addr);
887 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
888 if (unlikely(r != 0))
889 return r;
890 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
891 &rdev->r600_blit.shader_gpu_addr);
892 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
885 if (r) {
886 DRM_ERROR("failed to pin blit object %d\n", r);
887 return r;
888 }
889
890 /* Enable IRQ */
891 r = r600_irq_init(rdev);
892 if (r) {

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938 return r;
939 }
940 return r;
941
942}
943
944int rv770_suspend(struct radeon_device *rdev)
945{
893 if (r) {
894 DRM_ERROR("failed to pin blit object %d\n", r);
895 return r;
896 }
897
898 /* Enable IRQ */
899 r = r600_irq_init(rdev);
900 if (r) {

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946 return r;
947 }
948 return r;
949
950}
951
952int rv770_suspend(struct radeon_device *rdev)
953{
954 int r;
955
946 /* FIXME: we should wait for ring to be empty */
947 r700_cp_stop(rdev);
948 rdev->cp.ready = false;
949 r600_wb_disable(rdev);
950 rv770_pcie_gart_disable(rdev);
951 /* unpin shaders bo */
956 /* FIXME: we should wait for ring to be empty */
957 r700_cp_stop(rdev);
958 rdev->cp.ready = false;
959 r600_wb_disable(rdev);
960 rv770_pcie_gart_disable(rdev);
961 /* unpin shaders bo */
952 radeon_object_unpin(rdev->r600_blit.shader_obj);
962 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
963 if (likely(r == 0)) {
964 radeon_bo_unpin(rdev->r600_blit.shader_obj);
965 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
966 }
953 return 0;
954}
955
956/* Plan is to move initialization in that function and use
957 * helper function so that radeon_device_init pretty much
958 * do nothing more than calling asic specific function. This
959 * should also allow to remove a bunch of callback function
960 * like vram_info.

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1006 /* Fence driver */
1007 r = radeon_fence_driver_init(rdev);
1008 if (r)
1009 return r;
1010 r = rv770_mc_init(rdev);
1011 if (r)
1012 return r;
1013 /* Memory manager */
967 return 0;
968}
969
970/* Plan is to move initialization in that function and use
971 * helper function so that radeon_device_init pretty much
972 * do nothing more than calling asic specific function. This
973 * should also allow to remove a bunch of callback function
974 * like vram_info.

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1020 /* Fence driver */
1021 r = radeon_fence_driver_init(rdev);
1022 if (r)
1023 return r;
1024 r = rv770_mc_init(rdev);
1025 if (r)
1026 return r;
1027 /* Memory manager */
1014 r = radeon_object_init(rdev);
1028 r = radeon_bo_init(rdev);
1015 if (r)
1016 return r;
1017
1018 r = radeon_irq_kms_init(rdev);
1019 if (r)
1020 return r;
1021
1022 rdev->cp.ring_obj = NULL;

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1077 radeon_ring_fini(rdev);
1078 r600_wb_fini(rdev);
1079 rv770_pcie_gart_fini(rdev);
1080 radeon_gem_fini(rdev);
1081 radeon_fence_driver_fini(rdev);
1082 radeon_clocks_fini(rdev);
1083 if (rdev->flags & RADEON_IS_AGP)
1084 radeon_agp_fini(rdev);
1029 if (r)
1030 return r;
1031
1032 r = radeon_irq_kms_init(rdev);
1033 if (r)
1034 return r;
1035
1036 rdev->cp.ring_obj = NULL;

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1091 radeon_ring_fini(rdev);
1092 r600_wb_fini(rdev);
1093 rv770_pcie_gart_fini(rdev);
1094 radeon_gem_fini(rdev);
1095 radeon_fence_driver_fini(rdev);
1096 radeon_clocks_fini(rdev);
1097 if (rdev->flags & RADEON_IS_AGP)
1098 radeon_agp_fini(rdev);
1085 radeon_object_fini(rdev);
1099 radeon_bo_fini(rdev);
1086 radeon_atombios_fini(rdev);
1087 kfree(rdev->bios);
1088 rdev->bios = NULL;
1089 radeon_dummy_page_fini(rdev);
1090}
1100 radeon_atombios_fini(rdev);
1101 kfree(rdev->bios);
1102 rdev->bios = NULL;
1103 radeon_dummy_page_fini(rdev);
1104}