rs600.c (a2d07b7438f015a0349bc9af3c96a8164549bbc5) rs600.c (90aca4d2740255bd130ea71a91530b9920c70abe)
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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142 rdev->irq.hpd[1] = false;
143 break;
144 default:
145 break;
146 }
147 }
148}
149
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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142 rdev->irq.hpd[1] = false;
143 break;
144 default:
145 break;
146 }
147 }
148}
149
150void rs600_bm_disable(struct radeon_device *rdev)
151{
152 u32 tmp;
153
154 /* disable bus mastering */
155 pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
156 pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
157 mdelay(1);
158}
159
160int rs600_asic_reset(struct radeon_device *rdev)
161{
162 u32 status, tmp;
163
164 struct rv515_mc_save save;
165
166 /* Stops all mc clients */
167 rv515_mc_stop(rdev, &save);
168 status = RREG32(R_000E40_RBBM_STATUS);
169 if (!G_000E40_GUI_ACTIVE(status)) {
170 return 0;
171 }
172 status = RREG32(R_000E40_RBBM_STATUS);
173 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
174 /* stop CP */
175 WREG32(RADEON_CP_CSQ_CNTL, 0);
176 tmp = RREG32(RADEON_CP_RB_CNTL);
177 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
178 WREG32(RADEON_CP_RB_RPTR_WR, 0);
179 WREG32(RADEON_CP_RB_WPTR, 0);
180 WREG32(RADEON_CP_RB_CNTL, tmp);
181 pci_save_state(rdev->pdev);
182 /* disable bus mastering */
183 rs600_bm_disable(rdev);
184 /* reset GA+VAP */
185 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
186 S_0000F0_SOFT_RESET_GA(1));
187 RREG32(R_0000F0_RBBM_SOFT_RESET);
188 mdelay(500);
189 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
190 mdelay(1);
191 status = RREG32(R_000E40_RBBM_STATUS);
192 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
193 /* reset CP */
194 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
195 RREG32(R_0000F0_RBBM_SOFT_RESET);
196 mdelay(500);
197 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
198 mdelay(1);
199 status = RREG32(R_000E40_RBBM_STATUS);
200 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
201 /* reset MC */
202 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));
203 RREG32(R_0000F0_RBBM_SOFT_RESET);
204 mdelay(500);
205 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
206 mdelay(1);
207 status = RREG32(R_000E40_RBBM_STATUS);
208 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
209 /* restore PCI & busmastering */
210 pci_restore_state(rdev->pdev);
211 /* Check if GPU is idle */
212 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
213 dev_err(rdev->dev, "failed to reset GPU\n");
214 rdev->gpu_lockup = true;
215 return -1;
216 }
217 rv515_mc_resume(rdev, &save);
218 dev_info(rdev->dev, "GPU reset succeed\n");
219 return 0;
220}
221
150/*
151 * GART.
152 */
153void rs600_gart_tlb_flush(struct radeon_device *rdev)
154{
155 uint32_t tmp;
156
157 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);

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449 return 0;
450 udelay(1);
451 }
452 return -1;
453}
454
455void rs600_gpu_init(struct radeon_device *rdev)
456{
222/*
223 * GART.
224 */
225void rs600_gart_tlb_flush(struct radeon_device *rdev)
226{
227 uint32_t tmp;
228
229 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);

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521 return 0;
522 udelay(1);
523 }
524 return -1;
525}
526
527void rs600_gpu_init(struct radeon_device *rdev)
528{
457 r100_hdp_reset(rdev);
458 r420_pipes_init(rdev);
459 /* Wait for mc idle */
460 if (rs600_mc_wait_for_idle(rdev))
461 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
462}
463
464void rs600_mc_init(struct radeon_device *rdev)
465{

--- 247 unchanged lines hidden --- 		529 r420_pipes_init(rdev);
530 /* Wait for mc idle */
531 if (rs600_mc_wait_for_idle(rdev))
532 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
533}
534
535void rs600_mc_init(struct radeon_device *rdev)
536{

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