radeon.h (e9723bf2ad1b7384e8d475e5356f51a1f35a8934) radeon.h (954605ca3f897ad617123279eb3404a404cce5ab)
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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60 * are considered as fatal)
61 */
62
63#include <linux/atomic.h>
64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67#include <linux/interval_tree.h>
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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60 * are considered as fatal)
61 */
62
63#include <linux/atomic.h>
64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67#include <linux/interval_tree.h>
68#include <linux/hashtable.h>
69#include <linux/fence.h>
68
69#include <ttm/ttm_bo_api.h>
70#include <ttm/ttm_bo_driver.h>
71#include <ttm/ttm_placement.h>
72#include <ttm/ttm_module.h>
73#include <ttm/ttm_execbuf_util.h>
74
75#include "radeon_family.h"

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114#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
115#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
116/* RADEON_IB_POOL_SIZE must be a power of 2 */
117#define RADEON_IB_POOL_SIZE 16
118#define RADEON_DEBUGFS_MAX_COMPONENTS 32
119#define RADEONFB_CONN_LIMIT 4
120#define RADEON_BIOS_NUM_SCRATCH 8
121
70
71#include <ttm/ttm_bo_api.h>
72#include <ttm/ttm_bo_driver.h>
73#include <ttm/ttm_placement.h>
74#include <ttm/ttm_module.h>
75#include <ttm/ttm_execbuf_util.h>
76
77#include "radeon_family.h"

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116#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
117#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
118/* RADEON_IB_POOL_SIZE must be a power of 2 */
119#define RADEON_IB_POOL_SIZE 16
120#define RADEON_DEBUGFS_MAX_COMPONENTS 32
121#define RADEONFB_CONN_LIMIT 4
122#define RADEON_BIOS_NUM_SCRATCH 8
123
122/* fence seq are set to this number when signaled */
123#define RADEON_FENCE_SIGNALED_SEQ 0LL
124
125/* internal ring indices */
126/* r1xx+ has gfx CP ring */
127#define RADEON_RING_TYPE_GFX_INDEX 0
128
129/* cayman has 2 compute CP rings */
130#define CAYMAN_RING_TYPE_CP1_INDEX 1
131#define CAYMAN_RING_TYPE_CP2_INDEX 2
132

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344extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
345 unsigned *bankh, unsigned *mtaspect,
346 unsigned *tile_split);
347
348/*
349 * Fences.
350 */
351struct radeon_fence_driver {
124/* internal ring indices */
125/* r1xx+ has gfx CP ring */
126#define RADEON_RING_TYPE_GFX_INDEX 0
127
128/* cayman has 2 compute CP rings */
129#define CAYMAN_RING_TYPE_CP1_INDEX 1
130#define CAYMAN_RING_TYPE_CP2_INDEX 2
131

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343extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
344 unsigned *bankh, unsigned *mtaspect,
345 unsigned *tile_split);
346
347/*
348 * Fences.
349 */
350struct radeon_fence_driver {
351 struct radeon_device *rdev;
352 uint32_t scratch_reg;
353 uint64_t gpu_addr;
354 volatile uint32_t *cpu_addr;
355 /* sync_seq is protected by ring emission lock */
356 uint64_t sync_seq[RADEON_NUM_RINGS];
357 atomic64_t last_seq;
352 uint32_t scratch_reg;
353 uint64_t gpu_addr;
354 volatile uint32_t *cpu_addr;
355 /* sync_seq is protected by ring emission lock */
356 uint64_t sync_seq[RADEON_NUM_RINGS];
357 atomic64_t last_seq;
358 bool initialized;
358 bool initialized, delayed_irq;
359 struct delayed_work lockup_work;
359};
360
361struct radeon_fence {
360};
361
362struct radeon_fence {
363 struct fence base;
364
362 struct radeon_device *rdev;
365 struct radeon_device *rdev;
363 struct kref kref;
364 /* protected by radeon_fence.lock */
365 uint64_t seq;
366 /* RB, DMA, etc. */
367 unsigned ring;
366 uint64_t seq;
367 /* RB, DMA, etc. */
368 unsigned ring;
369
370 wait_queue_t fence_wake;
368};
369
370int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
371int radeon_fence_driver_init(struct radeon_device *rdev);
372void radeon_fence_driver_fini(struct radeon_device *rdev);
371};
372
373int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
374int radeon_fence_driver_init(struct radeon_device *rdev);
375void radeon_fence_driver_fini(struct radeon_device *rdev);
373void radeon_fence_driver_force_completion(struct radeon_device *rdev);
376void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
374int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
375void radeon_fence_process(struct radeon_device *rdev, int ring);
376bool radeon_fence_signaled(struct radeon_fence *fence);
377int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
378int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
379int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
380int radeon_fence_wait_any(struct radeon_device *rdev,
381 struct radeon_fence **fences,

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463 struct radeon_bo *bo;
464};
465
466struct radeon_bo {
467 /* Protected by gem.mutex */
468 struct list_head list;
469 /* Protected by tbo.reserved */
470 u32 initial_domain;
377int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
378void radeon_fence_process(struct radeon_device *rdev, int ring);
379bool radeon_fence_signaled(struct radeon_fence *fence);
380int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
381int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
382int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
383int radeon_fence_wait_any(struct radeon_device *rdev,
384 struct radeon_fence **fences,

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466 struct radeon_bo *bo;
467};
468
469struct radeon_bo {
470 /* Protected by gem.mutex */
471 struct list_head list;
472 /* Protected by tbo.reserved */
473 u32 initial_domain;
471 u32 placements[3];
474 struct ttm_place placements[3];
472 struct ttm_placement placement;
473 struct ttm_buffer_object tbo;
474 struct ttm_bo_kmap_obj kmap;
475 u32 flags;
476 unsigned pin_count;
477 void *kptr;
478 u32 tiling_flags;
479 u32 pitch;
480 int surface_reg;
481 /* list of all virtual address to which this bo
482 * is associated to
483 */
484 struct list_head va;
485 /* Constant after initialization */
486 struct radeon_device *rdev;
487 struct drm_gem_object gem_base;
488
489 struct ttm_bo_kmap_obj dma_buf_vmap;
490 pid_t pid;
475 struct ttm_placement placement;
476 struct ttm_buffer_object tbo;
477 struct ttm_bo_kmap_obj kmap;
478 u32 flags;
479 unsigned pin_count;
480 void *kptr;
481 u32 tiling_flags;
482 u32 pitch;
483 int surface_reg;
484 /* list of all virtual address to which this bo
485 * is associated to
486 */
487 struct list_head va;
488 /* Constant after initialization */
489 struct radeon_device *rdev;
490 struct drm_gem_object gem_base;
491
492 struct ttm_bo_kmap_obj dma_buf_vmap;
493 pid_t pid;
494
495 struct radeon_mn *mn;
496 struct interval_tree_node mn_it;
491};
492#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
493
494int radeon_gem_debugfs_init(struct radeon_device *rdev);
495
496/* sub-allocation manager, it has to be protected by another lock.
497 * By conception this is an helper for other part of the driver
498 * like the indirect buffer or semaphore, which both have their

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774 bool afmt[RADEON_MAX_AFMT_BLOCKS];
775 union radeon_irq_stat_regs stat_regs;
776 bool dpm_thermal;
777};
778
779int radeon_irq_kms_init(struct radeon_device *rdev);
780void radeon_irq_kms_fini(struct radeon_device *rdev);
781void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
497};
498#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
499
500int radeon_gem_debugfs_init(struct radeon_device *rdev);
501
502/* sub-allocation manager, it has to be protected by another lock.
503 * By conception this is an helper for other part of the driver
504 * like the indirect buffer or semaphore, which both have their

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780 bool afmt[RADEON_MAX_AFMT_BLOCKS];
781 union radeon_irq_stat_regs stat_regs;
782 bool dpm_thermal;
783};
784
785int radeon_irq_kms_init(struct radeon_device *rdev);
786void radeon_irq_kms_fini(struct radeon_device *rdev);
787void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
788bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
782void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
783void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
784void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
785void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
786void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
787void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
788void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
789

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910 struct radeon_fence *active[RADEON_NUM_VM];
911 uint32_t max_pfn;
912 /* number of VMIDs */
913 unsigned nvm;
914 /* vram base address for page table entry */
915 u64 vram_base_offset;
916 /* is vm enabled? */
917 bool enabled;
789void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
790void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
791void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
792void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
793void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
794void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
795void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
796

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917 struct radeon_fence *active[RADEON_NUM_VM];
918 uint32_t max_pfn;
919 /* number of VMIDs */
920 unsigned nvm;
921 /* vram base address for page table entry */
922 u64 vram_base_offset;
923 /* is vm enabled? */
924 bool enabled;
918 /* for hw to save the PD addr on suspend/resume */
919 uint32_t saved_table_addr[RADEON_NUM_VM];
920};
921
922/*
923 * file private structure
924 */
925struct radeon_fpriv {
926 struct radeon_vm vm;
927};

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1636int radeon_uvd_init(struct radeon_device *rdev);
1637void radeon_uvd_fini(struct radeon_device *rdev);
1638int radeon_uvd_suspend(struct radeon_device *rdev);
1639int radeon_uvd_resume(struct radeon_device *rdev);
1640int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1641 uint32_t handle, struct radeon_fence **fence);
1642int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1643 uint32_t handle, struct radeon_fence **fence);
925};
926
927/*
928 * file private structure
929 */
930struct radeon_fpriv {
931 struct radeon_vm vm;
932};

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1641int radeon_uvd_init(struct radeon_device *rdev);
1642void radeon_uvd_fini(struct radeon_device *rdev);
1643int radeon_uvd_suspend(struct radeon_device *rdev);
1644int radeon_uvd_resume(struct radeon_device *rdev);
1645int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1646 uint32_t handle, struct radeon_fence **fence);
1647int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1648 uint32_t handle, struct radeon_fence **fence);
1644void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1649void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1650 uint32_t allowed_domains);
1645void radeon_uvd_free_handles(struct radeon_device *rdev,
1646 struct drm_file *filp);
1647int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1648void radeon_uvd_note_usage(struct radeon_device *rdev);
1649int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1650 unsigned vclk, unsigned dclk,
1651 unsigned vco_min, unsigned vco_max,
1652 unsigned fb_factor, unsigned fb_mask,

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1725 * Testing
1726 */
1727void radeon_test_moves(struct radeon_device *rdev);
1728void radeon_test_ring_sync(struct radeon_device *rdev,
1729 struct radeon_ring *cpA,
1730 struct radeon_ring *cpB);
1731void radeon_test_syncing(struct radeon_device *rdev);
1732
1651void radeon_uvd_free_handles(struct radeon_device *rdev,
1652 struct drm_file *filp);
1653int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1654void radeon_uvd_note_usage(struct radeon_device *rdev);
1655int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1656 unsigned vclk, unsigned dclk,
1657 unsigned vco_min, unsigned vco_max,
1658 unsigned fb_factor, unsigned fb_mask,

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1731 * Testing
1732 */
1733void radeon_test_moves(struct radeon_device *rdev);
1734void radeon_test_ring_sync(struct radeon_device *rdev,
1735 struct radeon_ring *cpA,
1736 struct radeon_ring *cpB);
1737void radeon_test_syncing(struct radeon_device *rdev);
1738
1739/*
1740 * MMU Notifier
1741 */
1742int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1743void radeon_mn_unregister(struct radeon_bo *bo);
1733
1734/*
1735 * Debugfs
1736 */
1737struct radeon_debugfs {
1738 struct drm_info_list *files;
1739 unsigned num_files;
1740};

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2138
2139/*
2140 * IOCTL.
2141 */
2142int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2143 struct drm_file *filp);
2144int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2145 struct drm_file *filp);
1744
1745/*
1746 * Debugfs
1747 */
1748struct radeon_debugfs {
1749 struct drm_info_list *files;
1750 unsigned num_files;
1751};

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2149
2150/*
2151 * IOCTL.
2152 */
2153int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2154 struct drm_file *filp);
2155int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2156 struct drm_file *filp);
2157int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2158 struct drm_file *filp);
2146int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2147 struct drm_file *file_priv);
2148int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2149 struct drm_file *file_priv);
2150int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2151 struct drm_file *file_priv);
2152int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2153 struct drm_file *file_priv);

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2294 struct radeon_mc mc;
2295 struct radeon_gart gart;
2296 struct radeon_mode_info mode_info;
2297 struct radeon_scratch scratch;
2298 struct radeon_doorbell doorbell;
2299 struct radeon_mman mman;
2300 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2301 wait_queue_head_t fence_queue;
2159int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2160 struct drm_file *file_priv);
2161int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2162 struct drm_file *file_priv);
2163int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2164 struct drm_file *file_priv);
2165int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2166 struct drm_file *file_priv);

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2307 struct radeon_mc mc;
2308 struct radeon_gart gart;
2309 struct radeon_mode_info mode_info;
2310 struct radeon_scratch scratch;
2311 struct radeon_doorbell doorbell;
2312 struct radeon_mman mman;
2313 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2314 wait_queue_head_t fence_queue;
2315 unsigned fence_context;
2302 struct mutex ring_lock;
2303 struct radeon_ring ring[RADEON_NUM_RINGS];
2304 bool ib_pool_ready;
2305 struct radeon_sa_manager ring_tmp_bo;
2306 struct radeon_irq irq;
2307 struct radeon_asic *asic;
2308 struct radeon_gem gem;
2309 struct radeon_pm pm;
2310 struct radeon_uvd uvd;
2311 struct radeon_vce vce;
2312 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2313 struct radeon_wb wb;
2314 struct radeon_dummy_page dummy_page;
2315 bool shutdown;
2316 bool suspend;
2317 bool need_dma32;
2318 bool accel_working;
2319 bool fastfb_working; /* IGP feature*/
2316 struct mutex ring_lock;
2317 struct radeon_ring ring[RADEON_NUM_RINGS];
2318 bool ib_pool_ready;
2319 struct radeon_sa_manager ring_tmp_bo;
2320 struct radeon_irq irq;
2321 struct radeon_asic *asic;
2322 struct radeon_gem gem;
2323 struct radeon_pm pm;
2324 struct radeon_uvd uvd;
2325 struct radeon_vce vce;
2326 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2327 struct radeon_wb wb;
2328 struct radeon_dummy_page dummy_page;
2329 bool shutdown;
2330 bool suspend;
2331 bool need_dma32;
2332 bool accel_working;
2333 bool fastfb_working; /* IGP feature*/
2320 bool needs_reset;
2334 bool needs_reset, in_reset;
2321 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2322 const struct firmware *me_fw; /* all family ME firmware */
2323 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2324 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2325 const struct firmware *mc_fw; /* NI MC firmware */
2326 const struct firmware *ce_fw; /* SI CE firmware */
2327 const struct firmware *mec_fw; /* CIK MEC firmware */
2328 const struct firmware *mec2_fw; /* KV MEC2 firmware */

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2333 bool new_fw;
2334 struct r600_vram_scratch vram_scratch;
2335 int msi_enabled; /* msi enabled */
2336 struct r600_ih ih; /* r6/700 interrupt ring */
2337 struct radeon_rlc rlc;
2338 struct radeon_mec mec;
2339 struct work_struct hotplug_work;
2340 struct work_struct audio_work;
2335 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2336 const struct firmware *me_fw; /* all family ME firmware */
2337 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2338 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2339 const struct firmware *mc_fw; /* NI MC firmware */
2340 const struct firmware *ce_fw; /* SI CE firmware */
2341 const struct firmware *mec_fw; /* CIK MEC firmware */
2342 const struct firmware *mec2_fw; /* KV MEC2 firmware */

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2347 bool new_fw;
2348 struct r600_vram_scratch vram_scratch;
2349 int msi_enabled; /* msi enabled */
2350 struct r600_ih ih; /* r6/700 interrupt ring */
2351 struct radeon_rlc rlc;
2352 struct radeon_mec mec;
2353 struct work_struct hotplug_work;
2354 struct work_struct audio_work;
2341 struct work_struct reset_work;
2342 int num_crtc; /* number of crtcs */
2343 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2344 bool has_uvd;
2345 struct r600_audio audio; /* audio stuff */
2346 struct notifier_block acpi_nb;
2347 /* only one userspace can use Hyperz features or CMASK at a time */
2348 struct drm_file *hyperz_filp;
2349 struct drm_file *cmask_filp;

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2370
2371 struct dev_pm_domain vga_pm_domain;
2372 bool have_disp_power_ref;
2373 u32 px_quirk_flags;
2374
2375 /* tracking pinned memory */
2376 u64 vram_pin_size;
2377 u64 gart_pin_size;
2355 int num_crtc; /* number of crtcs */
2356 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2357 bool has_uvd;
2358 struct r600_audio audio; /* audio stuff */
2359 struct notifier_block acpi_nb;
2360 /* only one userspace can use Hyperz features or CMASK at a time */
2361 struct drm_file *hyperz_filp;
2362 struct drm_file *cmask_filp;

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2383
2384 struct dev_pm_domain vga_pm_domain;
2385 bool have_disp_power_ref;
2386 u32 px_quirk_flags;
2387
2388 /* tracking pinned memory */
2389 u64 vram_pin_size;
2390 u64 gart_pin_size;
2391
2392 struct mutex mn_lock;
2393 DECLARE_HASHTABLE(mn_hash, 7);
2378};
2379
2380bool radeon_is_px(struct drm_device *dev);
2381int radeon_device_init(struct radeon_device *rdev,
2382 struct drm_device *ddev,
2383 struct pci_dev *pdev,
2384 uint32_t flags);
2385void radeon_device_fini(struct radeon_device *rdev);

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2425void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2426
2427u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2428void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2429
2430/*
2431 * Cast helper
2432 */
2394};
2395
2396bool radeon_is_px(struct drm_device *dev);
2397int radeon_device_init(struct radeon_device *rdev,
2398 struct drm_device *ddev,
2399 struct pci_dev *pdev,
2400 uint32_t flags);
2401void radeon_device_fini(struct radeon_device *rdev);

--- 39 unchanged lines hidden (view full) ---

2441void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2442
2443u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2444void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2445
2446/*
2447 * Cast helper
2448 */
2433#define to_radeon_fence(p) ((struct radeon_fence *)(p))
2449extern const struct fence_ops radeon_fence_ops;
2434
2450
2451static inline struct radeon_fence *to_radeon_fence(struct fence *f)
2452{
2453 struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2454
2455 if (__f->base.ops == &radeon_fence_ops)
2456 return __f;
2457
2458 return NULL;
2459}
2460
2435/*
2436 * Registers read & write functions.
2437 */
2438#define RREG8(reg) readb((rdev->rmmio) + (reg))
2439#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2440#define RREG16(reg) readw((rdev->rmmio) + (reg))
2441#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2442#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)

--- 428 unchanged lines hidden (view full) ---

2871extern int radeon_wb_init(struct radeon_device *rdev);
2872extern void radeon_wb_disable(struct radeon_device *rdev);
2873extern void radeon_surface_init(struct radeon_device *rdev);
2874extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2875extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2876extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2877extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2878extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2461/*
2462 * Registers read & write functions.
2463 */
2464#define RREG8(reg) readb((rdev->rmmio) + (reg))
2465#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2466#define RREG16(reg) readw((rdev->rmmio) + (reg))
2467#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2468#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)

--- 428 unchanged lines hidden (view full) ---

2897extern int radeon_wb_init(struct radeon_device *rdev);
2898extern void radeon_wb_disable(struct radeon_device *rdev);
2899extern void radeon_surface_init(struct radeon_device *rdev);
2900extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2901extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2902extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2903extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2904extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2905extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2906 uint32_t flags);
2907extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
2908extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
2879extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2880extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2881extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2882extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2883extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2884extern void radeon_program_register_sequence(struct radeon_device *rdev,
2885 const u32 *registers,
2886 const u32 array_size);

--- 131 unchanged lines hidden --- 		2909extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2910extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2911extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2912extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2913extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2914extern void radeon_program_register_sequence(struct radeon_device *rdev,
2915 const u32 *registers,
2916 const u32 array_size);

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