radeon.h (9f48c89862e39b7f33b44123fc425cf901c89428) radeon.h (1c0a46255f8d7daf5b601668836e185fd1294e94)
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63#include <linux/atomic.h>
64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63#include <linux/atomic.h>
64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67#include <linux/interval_tree.h>
68#include <linux/hashtable.h>
69#include <linux/fence.h>
67
68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
72#include <ttm/ttm_execbuf_util.h>
73
70
71#include <ttm/ttm_bo_api.h>
72#include <ttm/ttm_bo_driver.h>
73#include <ttm/ttm_placement.h>
74#include <ttm/ttm_module.h>
75#include <ttm/ttm_execbuf_util.h>
76
77#include <drm/drm_gem.h>
78
74#include "radeon_family.h"
75#include "radeon_mode.h"
76#include "radeon_reg.h"
77
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;

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98extern int radeon_fastfb;
99extern int radeon_dpm;
100extern int radeon_aspm;
101extern int radeon_runtime_pm;
102extern int radeon_hard_reset;
103extern int radeon_vm_size;
104extern int radeon_vm_block_size;
105extern int radeon_deep_color;
79#include "radeon_family.h"
80#include "radeon_mode.h"
81#include "radeon_reg.h"
82
83/*
84 * Modules parameters.
85 */
86extern int radeon_no_wb;

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103extern int radeon_fastfb;
104extern int radeon_dpm;
105extern int radeon_aspm;
106extern int radeon_runtime_pm;
107extern int radeon_hard_reset;
108extern int radeon_vm_size;
109extern int radeon_vm_block_size;
110extern int radeon_deep_color;
111extern int radeon_use_pflipirq;
112extern int radeon_bapm;
113extern int radeon_backlight;
106
107/*
108 * Copy from radeon_drv.h so we don't have to include both and have conflicting
109 * symbol;
110 */
111#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
112#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
113/* RADEON_IB_POOL_SIZE must be a power of 2 */
114#define RADEON_IB_POOL_SIZE 16
115#define RADEON_DEBUGFS_MAX_COMPONENTS 32
116#define RADEONFB_CONN_LIMIT 4
117#define RADEON_BIOS_NUM_SCRATCH 8
118
114
115/*
116 * Copy from radeon_drv.h so we don't have to include both and have conflicting
117 * symbol;
118 */
119#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
120#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
121/* RADEON_IB_POOL_SIZE must be a power of 2 */
122#define RADEON_IB_POOL_SIZE 16
123#define RADEON_DEBUGFS_MAX_COMPONENTS 32
124#define RADEONFB_CONN_LIMIT 4
125#define RADEON_BIOS_NUM_SCRATCH 8
126
119/* fence seq are set to this number when signaled */
120#define RADEON_FENCE_SIGNALED_SEQ 0LL
121
122/* internal ring indices */
123/* r1xx+ has gfx CP ring */
124#define RADEON_RING_TYPE_GFX_INDEX 0
125
126/* cayman has 2 compute CP rings */
127#define CAYMAN_RING_TYPE_CP1_INDEX 1
128#define CAYMAN_RING_TYPE_CP2_INDEX 2
129

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299 u16 *voltage,
300 u16 leakage_idx);
301int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
302 u16 *leakage_id);
303int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
304 u16 *vddc, u16 *vddci,
305 u16 virtual_voltage_id,
306 u16 vbios_voltage_id);
127/* internal ring indices */
128/* r1xx+ has gfx CP ring */
129#define RADEON_RING_TYPE_GFX_INDEX 0
130
131/* cayman has 2 compute CP rings */
132#define CAYMAN_RING_TYPE_CP1_INDEX 1
133#define CAYMAN_RING_TYPE_CP2_INDEX 2
134

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304 u16 *voltage,
305 u16 leakage_idx);
306int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
307 u16 *leakage_id);
308int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
309 u16 *vddc, u16 *vddci,
310 u16 virtual_voltage_id,
311 u16 vbios_voltage_id);
312int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
313 u16 virtual_voltage_id,
314 u16 *voltage);
307int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
308 u8 voltage_type,
309 u16 nominal_voltage,
310 u16 *true_voltage);
311int radeon_atom_get_min_voltage(struct radeon_device *rdev,
312 u8 voltage_type, u16 *min_voltage);
313int radeon_atom_get_max_voltage(struct radeon_device *rdev,
314 u8 voltage_type, u16 *max_voltage);
315int radeon_atom_get_voltage_table(struct radeon_device *rdev,
316 u8 voltage_type, u8 voltage_mode,
317 struct atom_voltage_table *voltage_table);
318bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
319 u8 voltage_type, u8 voltage_mode);
315int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
316 u8 voltage_type,
317 u16 nominal_voltage,
318 u16 *true_voltage);
319int radeon_atom_get_min_voltage(struct radeon_device *rdev,
320 u8 voltage_type, u16 *min_voltage);
321int radeon_atom_get_max_voltage(struct radeon_device *rdev,
322 u8 voltage_type, u16 *max_voltage);
323int radeon_atom_get_voltage_table(struct radeon_device *rdev,
324 u8 voltage_type, u8 voltage_mode,
325 struct atom_voltage_table *voltage_table);
326bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
327 u8 voltage_type, u8 voltage_mode);
328int radeon_atom_get_svi2_info(struct radeon_device *rdev,
329 u8 voltage_type,
330 u8 *svd_gpio_id, u8 *svc_gpio_id);
320void radeon_atom_update_memory_dll(struct radeon_device *rdev,
321 u32 mem_clock);
322void radeon_atom_set_ac_timing(struct radeon_device *rdev,
323 u32 mem_clock);
324int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
325 u8 module_index,
326 struct atom_mc_reg_table *reg_table);
327int radeon_atom_get_memory_info(struct radeon_device *rdev,

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335extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
336 unsigned *bankh, unsigned *mtaspect,
337 unsigned *tile_split);
338
339/*
340 * Fences.
341 */
342struct radeon_fence_driver {
331void radeon_atom_update_memory_dll(struct radeon_device *rdev,
332 u32 mem_clock);
333void radeon_atom_set_ac_timing(struct radeon_device *rdev,
334 u32 mem_clock);
335int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
336 u8 module_index,
337 struct atom_mc_reg_table *reg_table);
338int radeon_atom_get_memory_info(struct radeon_device *rdev,

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346extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
347 unsigned *bankh, unsigned *mtaspect,
348 unsigned *tile_split);
349
350/*
351 * Fences.
352 */
353struct radeon_fence_driver {
354 struct radeon_device *rdev;
343 uint32_t scratch_reg;
344 uint64_t gpu_addr;
345 volatile uint32_t *cpu_addr;
346 /* sync_seq is protected by ring emission lock */
347 uint64_t sync_seq[RADEON_NUM_RINGS];
348 atomic64_t last_seq;
355 uint32_t scratch_reg;
356 uint64_t gpu_addr;
357 volatile uint32_t *cpu_addr;
358 /* sync_seq is protected by ring emission lock */
359 uint64_t sync_seq[RADEON_NUM_RINGS];
360 atomic64_t last_seq;
349 bool initialized;
361 bool initialized, delayed_irq;
362 struct delayed_work lockup_work;
350};
351
352struct radeon_fence {
363};
364
365struct radeon_fence {
366 struct fence base;
367
353 struct radeon_device *rdev;
368 struct radeon_device *rdev;
354 struct kref kref;
355 /* protected by radeon_fence.lock */
356 uint64_t seq;
357 /* RB, DMA, etc. */
358 unsigned ring;
369 uint64_t seq;
370 /* RB, DMA, etc. */
371 unsigned ring;
372
373 wait_queue_t fence_wake;
359};
360
361int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
362int radeon_fence_driver_init(struct radeon_device *rdev);
363void radeon_fence_driver_fini(struct radeon_device *rdev);
374};
375
376int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
377int radeon_fence_driver_init(struct radeon_device *rdev);
378void radeon_fence_driver_fini(struct radeon_device *rdev);
364void radeon_fence_driver_force_completion(struct radeon_device *rdev);
379void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
365int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
366void radeon_fence_process(struct radeon_device *rdev, int ring);
367bool radeon_fence_signaled(struct radeon_fence *fence);
368int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
369int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
370int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
371int radeon_fence_wait_any(struct radeon_device *rdev,
372 struct radeon_fence **fences,

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436 struct dentry *gtt;
437#endif
438};
439
440/* bo virtual address in a specific vm */
441struct radeon_bo_va {
442 /* protected by bo being reserved */
443 struct list_head bo_list;
380int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
381void radeon_fence_process(struct radeon_device *rdev, int ring);
382bool radeon_fence_signaled(struct radeon_fence *fence);
383int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
384int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
385int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
386int radeon_fence_wait_any(struct radeon_device *rdev,
387 struct radeon_fence **fences,

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451 struct dentry *gtt;
452#endif
453};
454
455/* bo virtual address in a specific vm */
456struct radeon_bo_va {
457 /* protected by bo being reserved */
458 struct list_head bo_list;
444 uint64_t soffset;
445 uint64_t eoffset;
446 uint32_t flags;
459 uint32_t flags;
447 bool valid;
460 uint64_t addr;
448 unsigned ref_count;
449
450 /* protected by vm mutex */
461 unsigned ref_count;
462
463 /* protected by vm mutex */
451 struct list_head vm_list;
464 struct interval_tree_node it;
465 struct list_head vm_status;
452
453 /* constant after initialization */
454 struct radeon_vm *vm;
455 struct radeon_bo *bo;
456};
457
458struct radeon_bo {
459 /* Protected by gem.mutex */
460 struct list_head list;
461 /* Protected by tbo.reserved */
462 u32 initial_domain;
466
467 /* constant after initialization */
468 struct radeon_vm *vm;
469 struct radeon_bo *bo;
470};
471
472struct radeon_bo {
473 /* Protected by gem.mutex */
474 struct list_head list;
475 /* Protected by tbo.reserved */
476 u32 initial_domain;
463 u32 placements[3];
477 struct ttm_place placements[4];
464 struct ttm_placement placement;
465 struct ttm_buffer_object tbo;
466 struct ttm_bo_kmap_obj kmap;
478 struct ttm_placement placement;
479 struct ttm_buffer_object tbo;
480 struct ttm_bo_kmap_obj kmap;
481 u32 flags;
467 unsigned pin_count;
468 void *kptr;
469 u32 tiling_flags;
470 u32 pitch;
471 int surface_reg;
472 /* list of all virtual address to which this bo
473 * is associated to
474 */
475 struct list_head va;
476 /* Constant after initialization */
477 struct radeon_device *rdev;
478 struct drm_gem_object gem_base;
479
480 struct ttm_bo_kmap_obj dma_buf_vmap;
481 pid_t pid;
482 unsigned pin_count;
483 void *kptr;
484 u32 tiling_flags;
485 u32 pitch;
486 int surface_reg;
487 /* list of all virtual address to which this bo
488 * is associated to
489 */
490 struct list_head va;
491 /* Constant after initialization */
492 struct radeon_device *rdev;
493 struct drm_gem_object gem_base;
494
495 struct ttm_bo_kmap_obj dma_buf_vmap;
496 pid_t pid;
497
498 struct radeon_mn *mn;
499 struct interval_tree_node mn_it;
482};
483#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
484
485int radeon_gem_debugfs_init(struct radeon_device *rdev);
486
487/* sub-allocation manager, it has to be protected by another lock.
488 * By conception this is an helper for other part of the driver
489 * like the indirect buffer or semaphore, which both have their

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537 */
538struct radeon_gem {
539 struct mutex mutex;
540 struct list_head objects;
541};
542
543int radeon_gem_init(struct radeon_device *rdev);
544void radeon_gem_fini(struct radeon_device *rdev);
500};
501#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
502
503int radeon_gem_debugfs_init(struct radeon_device *rdev);
504
505/* sub-allocation manager, it has to be protected by another lock.
506 * By conception this is an helper for other part of the driver
507 * like the indirect buffer or semaphore, which both have their

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555 */
556struct radeon_gem {
557 struct mutex mutex;
558 struct list_head objects;
559};
560
561int radeon_gem_init(struct radeon_device *rdev);
562void radeon_gem_fini(struct radeon_device *rdev);
545int radeon_gem_object_create(struct radeon_device *rdev, int size,
563int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
546 int alignment, int initial_domain,
564 int alignment, int initial_domain,
547 bool discardable, bool kernel,
565 u32 flags, bool kernel,
548 struct drm_gem_object **obj);
549
550int radeon_mode_dumb_create(struct drm_file *file_priv,
551 struct drm_device *dev,
552 struct drm_mode_create_dumb *args);
553int radeon_mode_dumb_mmap(struct drm_file *filp,
554 struct drm_device *dev,
555 uint32_t handle, uint64_t *offset_p);

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565};
566
567int radeon_semaphore_create(struct radeon_device *rdev,
568 struct radeon_semaphore **semaphore);
569bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
570 struct radeon_semaphore *semaphore);
571bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
572 struct radeon_semaphore *semaphore);
566 struct drm_gem_object **obj);
567
568int radeon_mode_dumb_create(struct drm_file *file_priv,
569 struct drm_device *dev,
570 struct drm_mode_create_dumb *args);
571int radeon_mode_dumb_mmap(struct drm_file *filp,
572 struct drm_device *dev,
573 uint32_t handle, uint64_t *offset_p);

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583};
584
585int radeon_semaphore_create(struct radeon_device *rdev,
586 struct radeon_semaphore **semaphore);
587bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
588 struct radeon_semaphore *semaphore);
589bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
590 struct radeon_semaphore *semaphore);
573void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore,
574 struct radeon_fence *fence);
591void radeon_semaphore_sync_fence(struct radeon_semaphore *semaphore,
592 struct radeon_fence *fence);
593int radeon_semaphore_sync_resv(struct radeon_device *rdev,
594 struct radeon_semaphore *semaphore,
595 struct reservation_object *resv,
596 bool shared);
575int radeon_semaphore_sync_rings(struct radeon_device *rdev,
576 struct radeon_semaphore *semaphore,
577 int waiting_ring);
578void radeon_semaphore_free(struct radeon_device *rdev,
579 struct radeon_semaphore **semaphore,
580 struct radeon_fence *fence);
581
582/*
583 * GART structures, functions & helpers
584 */
585struct radeon_mc;
586
587#define RADEON_GPU_PAGE_SIZE 4096
588#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
589#define RADEON_GPU_PAGE_SHIFT 12
590#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
591
597int radeon_semaphore_sync_rings(struct radeon_device *rdev,
598 struct radeon_semaphore *semaphore,
599 int waiting_ring);
600void radeon_semaphore_free(struct radeon_device *rdev,
601 struct radeon_semaphore **semaphore,
602 struct radeon_fence *fence);
603
604/*
605 * GART structures, functions & helpers
606 */
607struct radeon_mc;
608
609#define RADEON_GPU_PAGE_SIZE 4096
610#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
611#define RADEON_GPU_PAGE_SHIFT 12
612#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
613
614#define RADEON_GART_PAGE_DUMMY 0
615#define RADEON_GART_PAGE_VALID (1 << 0)
616#define RADEON_GART_PAGE_READ (1 << 1)
617#define RADEON_GART_PAGE_WRITE (1 << 2)
618#define RADEON_GART_PAGE_SNOOP (1 << 3)
619
592struct radeon_gart {
593 dma_addr_t table_addr;
594 struct radeon_bo *robj;
595 void *ptr;
596 unsigned num_gpu_pages;
597 unsigned num_cpu_pages;
598 unsigned table_size;
599 struct page **pages;

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608int radeon_gart_table_vram_pin(struct radeon_device *rdev);
609void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
610int radeon_gart_init(struct radeon_device *rdev);
611void radeon_gart_fini(struct radeon_device *rdev);
612void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
613 int pages);
614int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
615 int pages, struct page **pagelist,
620struct radeon_gart {
621 dma_addr_t table_addr;
622 struct radeon_bo *robj;
623 void *ptr;
624 unsigned num_gpu_pages;
625 unsigned num_cpu_pages;
626 unsigned table_size;
627 struct page **pages;

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636int radeon_gart_table_vram_pin(struct radeon_device *rdev);
637void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
638int radeon_gart_init(struct radeon_device *rdev);
639void radeon_gart_fini(struct radeon_device *rdev);
640void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
641 int pages);
642int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
643 int pages, struct page **pagelist,
616 dma_addr_t *dma_addr);
617void radeon_gart_restore(struct radeon_device *rdev);
644 dma_addr_t *dma_addr, uint32_t flags);
618
619
620/*
621 * GPU MC structures, functions & helpers
622 */
623struct radeon_mc {
624 resource_size_t aper_size;
625 resource_size_t aper_base;

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669 resource_size_t size;
670 u32 __iomem *ptr;
671 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
672 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
673};
674
675int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
676void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
645
646
647/*
648 * GPU MC structures, functions & helpers
649 */
650struct radeon_mc {
651 resource_size_t aper_size;
652 resource_size_t aper_base;

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696 resource_size_t size;
697 u32 __iomem *ptr;
698 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
699 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
700};
701
702int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
703void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
704void radeon_doorbell_get_kfd_info(struct radeon_device *rdev,
705 phys_addr_t *aperture_base,
706 size_t *aperture_size,
707 size_t *start_offset);
677
678/*
679 * IRQS.
680 */
681
682struct radeon_flip_work {
683 struct work_struct flip_work;
684 struct work_struct unpin_work;
685 struct radeon_device *rdev;
686 int crtc_id;
708
709/*
710 * IRQS.
711 */
712
713struct radeon_flip_work {
714 struct work_struct flip_work;
715 struct work_struct unpin_work;
716 struct radeon_device *rdev;
717 int crtc_id;
687 struct drm_framebuffer *fb;
718 uint64_t base;
688 struct drm_pending_vblank_event *event;
689 struct radeon_bo *old_rbo;
719 struct drm_pending_vblank_event *event;
720 struct radeon_bo *old_rbo;
690 struct radeon_bo *new_rbo;
691 struct radeon_fence *fence;
721 struct fence *fence;
692};
693
694struct r500_irq_stat_regs {
695 u32 disp_int;
696 u32 hdmi0_status;
697};
698
699struct r600_irq_stat_regs {

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761 bool afmt[RADEON_MAX_AFMT_BLOCKS];
762 union radeon_irq_stat_regs stat_regs;
763 bool dpm_thermal;
764};
765
766int radeon_irq_kms_init(struct radeon_device *rdev);
767void radeon_irq_kms_fini(struct radeon_device *rdev);
768void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
722};
723
724struct r500_irq_stat_regs {
725 u32 disp_int;
726 u32 hdmi0_status;
727};
728
729struct r600_irq_stat_regs {

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791 bool afmt[RADEON_MAX_AFMT_BLOCKS];
792 union radeon_irq_stat_regs stat_regs;
793 bool dpm_thermal;
794};
795
796int radeon_irq_kms_init(struct radeon_device *rdev);
797void radeon_irq_kms_fini(struct radeon_device *rdev);
798void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
799bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
769void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
770void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
771void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
772void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
773void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
774void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
775void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
776

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850#define R600_PTE_READABLE (1 << 5)
851#define R600_PTE_WRITEABLE (1 << 6)
852
853/* PTE (Page Table Entry) fragment field for different page sizes */
854#define R600_PTE_FRAG_4KB (0 << 7)
855#define R600_PTE_FRAG_64KB (4 << 7)
856#define R600_PTE_FRAG_256KB (6 << 7)
857
800void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
801void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
802void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
803void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
804void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
805void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
806void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
807

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881#define R600_PTE_READABLE (1 << 5)
882#define R600_PTE_WRITEABLE (1 << 6)
883
884/* PTE (Page Table Entry) fragment field for different page sizes */
885#define R600_PTE_FRAG_4KB (0 << 7)
886#define R600_PTE_FRAG_64KB (4 << 7)
887#define R600_PTE_FRAG_256KB (6 << 7)
888
858/* flags used for GART page table entries on R600+ */
859#define R600_PTE_GART ( R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED \
860 | R600_PTE_READABLE | R600_PTE_WRITEABLE)
889/* flags needed to be set so we can copy directly from the GART table */
890#define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
891 R600_PTE_SYSTEM | R600_PTE_VALID )
861
862struct radeon_vm_pt {
863 struct radeon_bo *bo;
864 uint64_t addr;
865};
866
867struct radeon_vm {
892
893struct radeon_vm_pt {
894 struct radeon_bo *bo;
895 uint64_t addr;
896};
897
898struct radeon_vm {
868 struct list_head va;
899 struct rb_root va;
869 unsigned id;
870
900 unsigned id;
901
902 /* BOs moved, but not yet updated in the PT */
903 struct list_head invalidated;
904
905 /* BOs freed, but not yet updated in the PT */
906 struct list_head freed;
907
871 /* contains the page directory */
872 struct radeon_bo *page_directory;
873 uint64_t pd_gpu_addr;
874 unsigned max_pde_used;
875
876 /* array of page tables, one for each page directory entry */
877 struct radeon_vm_pt *page_tables;
878
908 /* contains the page directory */
909 struct radeon_bo *page_directory;
910 uint64_t pd_gpu_addr;
911 unsigned max_pde_used;
912
913 /* array of page tables, one for each page directory entry */
914 struct radeon_vm_pt *page_tables;
915
916 struct radeon_bo_va *ib_bo_va;
917
879 struct mutex mutex;
880 /* last fence for cs using this vm */
881 struct radeon_fence *fence;
882 /* last flush or NULL if we still need to flush */
883 struct radeon_fence *last_flush;
884 /* last use of vmid */
885 struct radeon_fence *last_id_use;
886};
887
888struct radeon_vm_manager {
889 struct radeon_fence *active[RADEON_NUM_VM];
890 uint32_t max_pfn;
891 /* number of VMIDs */
892 unsigned nvm;
893 /* vram base address for page table entry */
894 u64 vram_base_offset;
895 /* is vm enabled? */
896 bool enabled;
918 struct mutex mutex;
919 /* last fence for cs using this vm */
920 struct radeon_fence *fence;
921 /* last flush or NULL if we still need to flush */
922 struct radeon_fence *last_flush;
923 /* last use of vmid */
924 struct radeon_fence *last_id_use;
925};
926
927struct radeon_vm_manager {
928 struct radeon_fence *active[RADEON_NUM_VM];
929 uint32_t max_pfn;
930 /* number of VMIDs */
931 unsigned nvm;
932 /* vram base address for page table entry */
933 u64 vram_base_offset;
934 /* is vm enabled? */
935 bool enabled;
936 /* for hw to save the PD addr on suspend/resume */
937 uint32_t saved_table_addr[RADEON_NUM_VM];
897};
898
899/*
900 * file private structure
901 */
902struct radeon_fpriv {
903 struct radeon_vm vm;
904};

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942 u32 cp_table_size;
943};
944
945int radeon_ib_get(struct radeon_device *rdev, int ring,
946 struct radeon_ib *ib, struct radeon_vm *vm,
947 unsigned size);
948void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
949int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
938};
939
940/*
941 * file private structure
942 */
943struct radeon_fpriv {
944 struct radeon_vm vm;
945};

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983 u32 cp_table_size;
984};
985
986int radeon_ib_get(struct radeon_device *rdev, int ring,
987 struct radeon_ib *ib, struct radeon_vm *vm,
988 unsigned size);
989void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
990int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
950 struct radeon_ib *const_ib);
991 struct radeon_ib *const_ib, bool hdp_flush);
951int radeon_ib_pool_init(struct radeon_device *rdev);
952void radeon_ib_pool_fini(struct radeon_device *rdev);
953int radeon_ib_ring_tests(struct radeon_device *rdev);
954/* Ring access between begin & end cannot sleep */
955bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
956 struct radeon_ring *ring);
957void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
958int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
959int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
992int radeon_ib_pool_init(struct radeon_device *rdev);
993void radeon_ib_pool_fini(struct radeon_device *rdev);
994int radeon_ib_ring_tests(struct radeon_device *rdev);
995/* Ring access between begin & end cannot sleep */
996bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
997 struct radeon_ring *ring);
998void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
999int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1000int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
960void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
961void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
1001void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1002 bool hdp_flush);
1003void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1004 bool hdp_flush);
962void radeon_ring_undo(struct radeon_ring *ring);
963void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
964int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
965void radeon_ring_lockup_update(struct radeon_device *rdev,
966 struct radeon_ring *ring);
967bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
968unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
969 uint32_t **data);

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1089#define RADEON_WB_CP1_RPTR_OFFSET 1280
1090#define RADEON_WB_CP2_RPTR_OFFSET 1536
1091#define R600_WB_DMA_RPTR_OFFSET 1792
1092#define R600_WB_IH_WPTR_OFFSET 2048
1093#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1094#define R600_WB_EVENT_OFFSET 3072
1095#define CIK_WB_CP1_WPTR_OFFSET 3328
1096#define CIK_WB_CP2_WPTR_OFFSET 3584
1005void radeon_ring_undo(struct radeon_ring *ring);
1006void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
1007int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
1008void radeon_ring_lockup_update(struct radeon_device *rdev,
1009 struct radeon_ring *ring);
1010bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
1011unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
1012 uint32_t **data);

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1132#define RADEON_WB_CP1_RPTR_OFFSET 1280
1133#define RADEON_WB_CP2_RPTR_OFFSET 1536
1134#define R600_WB_DMA_RPTR_OFFSET 1792
1135#define R600_WB_IH_WPTR_OFFSET 2048
1136#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1137#define R600_WB_EVENT_OFFSET 3072
1138#define CIK_WB_CP1_WPTR_OFFSET 3328
1139#define CIK_WB_CP2_WPTR_OFFSET 3584
1140#define R600_WB_DMA_RING_TEST_OFFSET 3588
1141#define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
1097
1098/**
1099 * struct radeon_pm - power management datas
1100 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1101 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1102 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1103 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1104 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)

--- 472 unchanged lines hidden (view full) ---

1577 bool dynpm_can_downclock;
1578 /* profile-based power management */
1579 enum radeon_pm_profile_type profile;
1580 int profile_index;
1581 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1582 /* internal thermal controller on rv6xx+ */
1583 enum radeon_int_thermal_type int_thermal_type;
1584 struct device *int_hwmon_dev;
1142
1143/**
1144 * struct radeon_pm - power management datas
1145 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1146 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1147 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1148 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1149 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)

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1622 bool dynpm_can_downclock;
1623 /* profile-based power management */
1624 enum radeon_pm_profile_type profile;
1625 int profile_index;
1626 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1627 /* internal thermal controller on rv6xx+ */
1628 enum radeon_int_thermal_type int_thermal_type;
1629 struct device *int_hwmon_dev;
1630 /* fan control parameters */
1631 bool no_fan;
1632 u8 fan_pulses_per_revolution;
1633 u8 fan_min_rpm;
1634 u8 fan_max_rpm;
1585 /* dpm */
1586 bool dpm_enabled;
1587 struct radeon_dpm dpm;
1588};
1589
1590int radeon_pm_get_type_index(struct radeon_device *rdev,
1591 enum radeon_pm_state_type ps_type,
1592 int instance);

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1611int radeon_uvd_init(struct radeon_device *rdev);
1612void radeon_uvd_fini(struct radeon_device *rdev);
1613int radeon_uvd_suspend(struct radeon_device *rdev);
1614int radeon_uvd_resume(struct radeon_device *rdev);
1615int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1616 uint32_t handle, struct radeon_fence **fence);
1617int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1618 uint32_t handle, struct radeon_fence **fence);
1635 /* dpm */
1636 bool dpm_enabled;
1637 struct radeon_dpm dpm;
1638};
1639
1640int radeon_pm_get_type_index(struct radeon_device *rdev,
1641 enum radeon_pm_state_type ps_type,
1642 int instance);

--- 18 unchanged lines hidden (view full) ---

1661int radeon_uvd_init(struct radeon_device *rdev);
1662void radeon_uvd_fini(struct radeon_device *rdev);
1663int radeon_uvd_suspend(struct radeon_device *rdev);
1664int radeon_uvd_resume(struct radeon_device *rdev);
1665int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1666 uint32_t handle, struct radeon_fence **fence);
1667int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1668 uint32_t handle, struct radeon_fence **fence);
1619void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1669void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1670 uint32_t allowed_domains);
1620void radeon_uvd_free_handles(struct radeon_device *rdev,
1621 struct drm_file *filp);
1622int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1623void radeon_uvd_note_usage(struct radeon_device *rdev);
1624int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1625 unsigned vclk, unsigned dclk,
1626 unsigned vco_min, unsigned vco_max,
1627 unsigned fb_factor, unsigned fb_mask,

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1700 * Testing
1701 */
1702void radeon_test_moves(struct radeon_device *rdev);
1703void radeon_test_ring_sync(struct radeon_device *rdev,
1704 struct radeon_ring *cpA,
1705 struct radeon_ring *cpB);
1706void radeon_test_syncing(struct radeon_device *rdev);
1707
1671void radeon_uvd_free_handles(struct radeon_device *rdev,
1672 struct drm_file *filp);
1673int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1674void radeon_uvd_note_usage(struct radeon_device *rdev);
1675int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1676 unsigned vclk, unsigned dclk,
1677 unsigned vco_min, unsigned vco_max,
1678 unsigned fb_factor, unsigned fb_mask,

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1751 * Testing
1752 */
1753void radeon_test_moves(struct radeon_device *rdev);
1754void radeon_test_ring_sync(struct radeon_device *rdev,
1755 struct radeon_ring *cpA,
1756 struct radeon_ring *cpB);
1757void radeon_test_syncing(struct radeon_device *rdev);
1758
1759/*
1760 * MMU Notifier
1761 */
1762int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1763void radeon_mn_unregister(struct radeon_bo *bo);
1708
1709/*
1710 * Debugfs
1711 */
1712struct radeon_debugfs {
1713 struct drm_info_list *files;
1714 unsigned num_files;
1715};

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1730
1731 /* validating and patching of IBs */
1732 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1733 int (*cs_parse)(struct radeon_cs_parser *p);
1734
1735 /* command emmit functions */
1736 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1737 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1764
1765/*
1766 * Debugfs
1767 */
1768struct radeon_debugfs {
1769 struct drm_info_list *files;
1770 unsigned num_files;
1771};

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1786
1787 /* validating and patching of IBs */
1788 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1789 int (*cs_parse)(struct radeon_cs_parser *p);
1790
1791 /* command emmit functions */
1792 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1793 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1794 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1738 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1739 struct radeon_semaphore *semaphore, bool emit_wait);
1740 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1741
1742 /* testing functions */
1743 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1744 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1745 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);

--- 7 unchanged lines hidden (view full) ---

1753 */
1754struct radeon_asic {
1755 int (*init)(struct radeon_device *rdev);
1756 void (*fini)(struct radeon_device *rdev);
1757 int (*resume)(struct radeon_device *rdev);
1758 int (*suspend)(struct radeon_device *rdev);
1759 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1760 int (*asic_reset)(struct radeon_device *rdev);
1795 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1796 struct radeon_semaphore *semaphore, bool emit_wait);
1797 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1798
1799 /* testing functions */
1800 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1801 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1802 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);

--- 7 unchanged lines hidden (view full) ---

1810 */
1811struct radeon_asic {
1812 int (*init)(struct radeon_device *rdev);
1813 void (*fini)(struct radeon_device *rdev);
1814 int (*resume)(struct radeon_device *rdev);
1815 int (*suspend)(struct radeon_device *rdev);
1816 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1817 int (*asic_reset)(struct radeon_device *rdev);
1761 /* ioctl hw specific callback. Some hw might want to perform special
1762 * operation on specific ioctl. For instance on wait idle some hw
1763 * might want to perform and HDP flush through MMIO as it seems that
1764 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1765 * through ring.
1766 */
1767 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1818 /* Flush the HDP cache via MMIO */
1819 void (*mmio_hdp_flush)(struct radeon_device *rdev);
1768 /* check if 3D engine is idle */
1769 bool (*gui_idle)(struct radeon_device *rdev);
1770 /* wait for mc_idle */
1771 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1772 /* get the reference clock */
1773 u32 (*get_xclk)(struct radeon_device *rdev);
1774 /* get the gpu clock counter */
1775 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1776 /* gart */
1777 struct {
1778 void (*tlb_flush)(struct radeon_device *rdev);
1779 void (*set_page)(struct radeon_device *rdev, unsigned i,
1820 /* check if 3D engine is idle */
1821 bool (*gui_idle)(struct radeon_device *rdev);
1822 /* wait for mc_idle */
1823 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1824 /* get the reference clock */
1825 u32 (*get_xclk)(struct radeon_device *rdev);
1826 /* get the gpu clock counter */
1827 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1828 /* gart */
1829 struct {
1830 void (*tlb_flush)(struct radeon_device *rdev);
1831 void (*set_page)(struct radeon_device *rdev, unsigned i,
1780 uint64_t addr);
1832 uint64_t addr, uint32_t flags);
1781 } gart;
1782 struct {
1783 int (*init)(struct radeon_device *rdev);
1784 void (*fini)(struct radeon_device *rdev);
1833 } gart;
1834 struct {
1835 int (*init)(struct radeon_device *rdev);
1836 void (*fini)(struct radeon_device *rdev);
1785 void (*set_page)(struct radeon_device *rdev,
1786 struct radeon_ib *ib,
1787 uint64_t pe,
1788 uint64_t addr, unsigned count,
1789 uint32_t incr, uint32_t flags);
1837 void (*copy_pages)(struct radeon_device *rdev,
1838 struct radeon_ib *ib,
1839 uint64_t pe, uint64_t src,
1840 unsigned count);
1841 void (*write_pages)(struct radeon_device *rdev,
1842 struct radeon_ib *ib,
1843 uint64_t pe,
1844 uint64_t addr, unsigned count,
1845 uint32_t incr, uint32_t flags);
1846 void (*set_pages)(struct radeon_device *rdev,
1847 struct radeon_ib *ib,
1848 uint64_t pe,
1849 uint64_t addr, unsigned count,
1850 uint32_t incr, uint32_t flags);
1851 void (*pad_ib)(struct radeon_ib *ib);
1790 } vm;
1791 /* ring specific callbacks */
1792 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1793 /* irqs */
1794 struct {
1795 int (*set)(struct radeon_device *rdev);
1796 int (*process)(struct radeon_device *rdev);
1797 } irq;

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1808 /* get backlight level */
1809 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1810 /* audio callbacks */
1811 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1812 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1813 } display;
1814 /* copy functions for bo handling */
1815 struct {
1852 } vm;
1853 /* ring specific callbacks */
1854 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1855 /* irqs */
1856 struct {
1857 int (*set)(struct radeon_device *rdev);
1858 int (*process)(struct radeon_device *rdev);
1859 } irq;

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1870 /* get backlight level */
1871 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1872 /* audio callbacks */
1873 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1874 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1875 } display;
1876 /* copy functions for bo handling */
1877 struct {
1816 int (*blit)(struct radeon_device *rdev,
1817 uint64_t src_offset,
1818 uint64_t dst_offset,
1819 unsigned num_gpu_pages,
1820 struct radeon_fence **fence);
1878 struct radeon_fence *(*blit)(struct radeon_device *rdev,
1879 uint64_t src_offset,
1880 uint64_t dst_offset,
1881 unsigned num_gpu_pages,
1882 struct reservation_object *resv);
1821 u32 blit_ring_index;
1883 u32 blit_ring_index;
1822 int (*dma)(struct radeon_device *rdev,
1823 uint64_t src_offset,
1824 uint64_t dst_offset,
1825 unsigned num_gpu_pages,
1826 struct radeon_fence **fence);
1884 struct radeon_fence *(*dma)(struct radeon_device *rdev,
1885 uint64_t src_offset,
1886 uint64_t dst_offset,
1887 unsigned num_gpu_pages,
1888 struct reservation_object *resv);
1827 u32 dma_ring_index;
1828 /* method used for bo copy */
1889 u32 dma_ring_index;
1890 /* method used for bo copy */
1829 int (*copy)(struct radeon_device *rdev,
1830 uint64_t src_offset,
1831 uint64_t dst_offset,
1832 unsigned num_gpu_pages,
1833 struct radeon_fence **fence);
1891 struct radeon_fence *(*copy)(struct radeon_device *rdev,
1892 uint64_t src_offset,
1893 uint64_t dst_offset,
1894 unsigned num_gpu_pages,
1895 struct reservation_object *resv);
1834 /* ring used for bo copies */
1835 u32 copy_ring_index;
1836 } copy;
1837 /* surfaces */
1838 struct {
1839 int (*set_reg)(struct radeon_device *rdev, int reg,
1840 uint32_t tiling_flags, uint32_t pitch,
1841 uint32_t offset, uint32_t obj_size);

--- 265 unchanged lines hidden (view full) ---

2107
2108/*
2109 * IOCTL.
2110 */
2111int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2112 struct drm_file *filp);
2113int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2114 struct drm_file *filp);
1896 /* ring used for bo copies */
1897 u32 copy_ring_index;
1898 } copy;
1899 /* surfaces */
1900 struct {
1901 int (*set_reg)(struct radeon_device *rdev, int reg,
1902 uint32_t tiling_flags, uint32_t pitch,
1903 uint32_t offset, uint32_t obj_size);

--- 265 unchanged lines hidden (view full) ---

2169
2170/*
2171 * IOCTL.
2172 */
2173int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2174 struct drm_file *filp);
2175int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2176 struct drm_file *filp);
2177int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2178 struct drm_file *filp);
2115int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2116 struct drm_file *file_priv);
2117int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2118 struct drm_file *file_priv);
2119int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2120 struct drm_file *file_priv);
2121int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2122 struct drm_file *file_priv);

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2263 struct radeon_mc mc;
2264 struct radeon_gart gart;
2265 struct radeon_mode_info mode_info;
2266 struct radeon_scratch scratch;
2267 struct radeon_doorbell doorbell;
2268 struct radeon_mman mman;
2269 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2270 wait_queue_head_t fence_queue;
2179int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2180 struct drm_file *file_priv);
2181int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2182 struct drm_file *file_priv);
2183int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2184 struct drm_file *file_priv);
2185int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2186 struct drm_file *file_priv);

--- 140 unchanged lines hidden (view full) ---

2327 struct radeon_mc mc;
2328 struct radeon_gart gart;
2329 struct radeon_mode_info mode_info;
2330 struct radeon_scratch scratch;
2331 struct radeon_doorbell doorbell;
2332 struct radeon_mman mman;
2333 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2334 wait_queue_head_t fence_queue;
2335 unsigned fence_context;
2271 struct mutex ring_lock;
2272 struct radeon_ring ring[RADEON_NUM_RINGS];
2273 bool ib_pool_ready;
2274 struct radeon_sa_manager ring_tmp_bo;
2275 struct radeon_irq irq;
2276 struct radeon_asic *asic;
2277 struct radeon_gem gem;
2278 struct radeon_pm pm;
2279 struct radeon_uvd uvd;
2280 struct radeon_vce vce;
2281 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2282 struct radeon_wb wb;
2283 struct radeon_dummy_page dummy_page;
2284 bool shutdown;
2285 bool suspend;
2286 bool need_dma32;
2287 bool accel_working;
2288 bool fastfb_working; /* IGP feature*/
2336 struct mutex ring_lock;
2337 struct radeon_ring ring[RADEON_NUM_RINGS];
2338 bool ib_pool_ready;
2339 struct radeon_sa_manager ring_tmp_bo;
2340 struct radeon_irq irq;
2341 struct radeon_asic *asic;
2342 struct radeon_gem gem;
2343 struct radeon_pm pm;
2344 struct radeon_uvd uvd;
2345 struct radeon_vce vce;
2346 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2347 struct radeon_wb wb;
2348 struct radeon_dummy_page dummy_page;
2349 bool shutdown;
2350 bool suspend;
2351 bool need_dma32;
2352 bool accel_working;
2353 bool fastfb_working; /* IGP feature*/
2289 bool needs_reset;
2354 bool needs_reset, in_reset;
2290 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2291 const struct firmware *me_fw; /* all family ME firmware */
2292 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2293 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2294 const struct firmware *mc_fw; /* NI MC firmware */
2295 const struct firmware *ce_fw; /* SI CE firmware */
2296 const struct firmware *mec_fw; /* CIK MEC firmware */
2355 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2356 const struct firmware *me_fw; /* all family ME firmware */
2357 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2358 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2359 const struct firmware *mc_fw; /* NI MC firmware */
2360 const struct firmware *ce_fw; /* SI CE firmware */
2361 const struct firmware *mec_fw; /* CIK MEC firmware */
2362 const struct firmware *mec2_fw; /* KV MEC2 firmware */
2297 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2298 const struct firmware *smc_fw; /* SMC firmware */
2299 const struct firmware *uvd_fw; /* UVD firmware */
2300 const struct firmware *vce_fw; /* VCE firmware */
2363 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2364 const struct firmware *smc_fw; /* SMC firmware */
2365 const struct firmware *uvd_fw; /* UVD firmware */
2366 const struct firmware *vce_fw; /* VCE firmware */
2367 bool new_fw;
2301 struct r600_vram_scratch vram_scratch;
2302 int msi_enabled; /* msi enabled */
2303 struct r600_ih ih; /* r6/700 interrupt ring */
2304 struct radeon_rlc rlc;
2305 struct radeon_mec mec;
2306 struct work_struct hotplug_work;
2307 struct work_struct audio_work;
2368 struct r600_vram_scratch vram_scratch;
2369 int msi_enabled; /* msi enabled */
2370 struct r600_ih ih; /* r6/700 interrupt ring */
2371 struct radeon_rlc rlc;
2372 struct radeon_mec mec;
2373 struct work_struct hotplug_work;
2374 struct work_struct audio_work;
2308 struct work_struct reset_work;
2309 int num_crtc; /* number of crtcs */
2310 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2311 bool has_uvd;
2312 struct r600_audio audio; /* audio stuff */
2313 struct notifier_block acpi_nb;
2314 /* only one userspace can use Hyperz features or CMASK at a time */
2315 struct drm_file *hyperz_filp;
2316 struct drm_file *cmask_filp;

--- 9 unchanged lines hidden (view full) ---

2326 atomic64_t vram_usage;
2327 atomic64_t gtt_usage;
2328 atomic64_t num_bytes_moved;
2329 /* ACPI interface */
2330 struct radeon_atif atif;
2331 struct radeon_atcs atcs;
2332 /* srbm instance registers */
2333 struct mutex srbm_mutex;
2375 int num_crtc; /* number of crtcs */
2376 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2377 bool has_uvd;
2378 struct r600_audio audio; /* audio stuff */
2379 struct notifier_block acpi_nb;
2380 /* only one userspace can use Hyperz features or CMASK at a time */
2381 struct drm_file *hyperz_filp;
2382 struct drm_file *cmask_filp;

--- 9 unchanged lines hidden (view full) ---

2392 atomic64_t vram_usage;
2393 atomic64_t gtt_usage;
2394 atomic64_t num_bytes_moved;
2395 /* ACPI interface */
2396 struct radeon_atif atif;
2397 struct radeon_atcs atcs;
2398 /* srbm instance registers */
2399 struct mutex srbm_mutex;
2400 /* GRBM index mutex. Protects concurrents access to GRBM index */
2401 struct mutex grbm_idx_mutex;
2334 /* clock, powergating flags */
2335 u32 cg_flags;
2336 u32 pg_flags;
2337
2338 struct dev_pm_domain vga_pm_domain;
2339 bool have_disp_power_ref;
2402 /* clock, powergating flags */
2403 u32 cg_flags;
2404 u32 pg_flags;
2405
2406 struct dev_pm_domain vga_pm_domain;
2407 bool have_disp_power_ref;
2408 u32 px_quirk_flags;
2409
2410 /* tracking pinned memory */
2411 u64 vram_pin_size;
2412 u64 gart_pin_size;
2413
2414 struct mutex mn_lock;
2415 DECLARE_HASHTABLE(mn_hash, 7);
2340};
2341
2342bool radeon_is_px(struct drm_device *dev);
2343int radeon_device_init(struct radeon_device *rdev,
2344 struct drm_device *ddev,
2345 struct pci_dev *pdev,
2346 uint32_t flags);
2347void radeon_device_fini(struct radeon_device *rdev);
2348int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2349
2416};
2417
2418bool radeon_is_px(struct drm_device *dev);
2419int radeon_device_init(struct radeon_device *rdev,
2420 struct drm_device *ddev,
2421 struct pci_dev *pdev,
2422 uint32_t flags);
2423void radeon_device_fini(struct radeon_device *rdev);
2424int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2425
2350uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2351 bool always_indirect);
2352void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2353 bool always_indirect);
2426#define RADEON_MIN_MMIO_SIZE 0x10000
2427
2428static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2429 bool always_indirect)
2430{
2431 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2432 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2433 return readl(((void __iomem *)rdev->rmmio) + reg);
2434 else {
2435 unsigned long flags;
2436 uint32_t ret;
2437
2438 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2439 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2440 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2441 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2442
2443 return ret;
2444 }
2445}
2446
2447static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2448 bool always_indirect)
2449{
2450 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2451 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2452 else {
2453 unsigned long flags;
2454
2455 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2456 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2457 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2458 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2459 }
2460}
2461
2354u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2355void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2356
2357u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2358void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2359
2360/*
2361 * Cast helper
2362 */
2462u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2463void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2464
2465u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2466void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2467
2468/*
2469 * Cast helper
2470 */
2363#define to_radeon_fence(p) ((struct radeon_fence *)(p))
2471extern const struct fence_ops radeon_fence_ops;
2364
2472
2473static inline struct radeon_fence *to_radeon_fence(struct fence *f)
2474{
2475 struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2476
2477 if (__f->base.ops == &radeon_fence_ops)
2478 return __f;
2479
2480 return NULL;
2481}
2482
2365/*
2366 * Registers read & write functions.
2367 */
2368#define RREG8(reg) readb((rdev->rmmio) + (reg))
2369#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2370#define RREG16(reg) readw((rdev->rmmio) + (reg))
2371#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2372#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)

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2675void radeon_combios_fini(struct radeon_device *rdev);
2676int radeon_atombios_init(struct radeon_device *rdev);
2677void radeon_atombios_fini(struct radeon_device *rdev);
2678
2679
2680/*
2681 * RING helpers.
2682 */
2483/*
2484 * Registers read & write functions.
2485 */
2486#define RREG8(reg) readb((rdev->rmmio) + (reg))
2487#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2488#define RREG16(reg) readw((rdev->rmmio) + (reg))
2489#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2490#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)

--- 302 unchanged lines hidden (view full) ---

2793void radeon_combios_fini(struct radeon_device *rdev);
2794int radeon_atombios_init(struct radeon_device *rdev);
2795void radeon_atombios_fini(struct radeon_device *rdev);
2796
2797
2798/*
2799 * RING helpers.
2800 */
2683#if DRM_DEBUG_CODE == 0
2801
2802/**
2803 * radeon_ring_write - write a value to the ring
2804 *
2805 * @ring: radeon_ring structure holding ring information
2806 * @v: dword (dw) value to write
2807 *
2808 * Write a value to the requested ring buffer (all asics).
2809 */
2684static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2685{
2810static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2811{
2812 if (ring->count_dw <= 0)
2813 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2814
2686 ring->ring[ring->wptr++] = v;
2687 ring->wptr &= ring->ptr_mask;
2688 ring->count_dw--;
2689 ring->ring_free_dw--;
2690}
2815 ring->ring[ring->wptr++] = v;
2816 ring->wptr &= ring->ptr_mask;
2817 ring->count_dw--;
2818 ring->ring_free_dw--;
2819}
2691#else
2692/* With debugging this is just too big to inline */
2693void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
2694#endif
2695
2696/*
2697 * ASICs macro.
2698 */
2699#define radeon_init(rdev) (rdev)->asic->init((rdev))
2700#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2701#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2702#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2703#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2704#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2705#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2706#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2820
2821/*
2822 * ASICs macro.
2823 */
2824#define radeon_init(rdev) (rdev)->asic->init((rdev))
2825#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2826#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2827#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2828#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2829#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2830#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2831#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2707#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
2832#define radeon_gart_set_page(rdev, i, p, f) (rdev)->asic->gart.set_page((rdev), (i), (p), (f))
2708#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2709#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2833#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2834#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2710#define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2835#define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2836#define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2837#define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2838#define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
2711#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2712#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2713#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2714#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2715#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2716#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2717#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2718#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2719#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2720#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2721#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2722#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2723#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2724#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2725#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2726#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2727#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2728#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2729#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2839#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2840#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2841#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2842#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2843#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2844#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2845#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2846#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2847#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2848#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2849#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2850#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2851#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2852#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2853#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2854#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2855#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2856#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2857#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2730#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2731#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2732#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2858#define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
2859#define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2860#define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
2733#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2734#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2735#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2736#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2737#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2738#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2739#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2740#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))

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2798extern int radeon_wb_init(struct radeon_device *rdev);
2799extern void radeon_wb_disable(struct radeon_device *rdev);
2800extern void radeon_surface_init(struct radeon_device *rdev);
2801extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2802extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2803extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2804extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2805extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2861#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2862#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2863#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2864#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2865#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2866#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2867#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2868#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))

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2926extern int radeon_wb_init(struct radeon_device *rdev);
2927extern void radeon_wb_disable(struct radeon_device *rdev);
2928extern void radeon_surface_init(struct radeon_device *rdev);
2929extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2930extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2931extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2932extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2933extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2934extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2935 uint32_t flags);
2936extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
2937extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
2806extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2807extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2808extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2809extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2810extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2811extern void radeon_program_register_sequence(struct radeon_device *rdev,
2812 const u32 *registers,
2813 const u32 array_size);

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2828 struct radeon_vm *vm,
2829 int ring);
2830void radeon_vm_fence(struct radeon_device *rdev,
2831 struct radeon_vm *vm,
2832 struct radeon_fence *fence);
2833uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2834int radeon_vm_update_page_directory(struct radeon_device *rdev,
2835 struct radeon_vm *vm);
2938extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2939extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2940extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2941extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2942extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2943extern void radeon_program_register_sequence(struct radeon_device *rdev,
2944 const u32 *registers,
2945 const u32 array_size);

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2960 struct radeon_vm *vm,
2961 int ring);
2962void radeon_vm_fence(struct radeon_device *rdev,
2963 struct radeon_vm *vm,
2964 struct radeon_fence *fence);
2965uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2966int radeon_vm_update_page_directory(struct radeon_device *rdev,
2967 struct radeon_vm *vm);
2968int radeon_vm_clear_freed(struct radeon_device *rdev,
2969 struct radeon_vm *vm);
2970int radeon_vm_clear_invalids(struct radeon_device *rdev,
2971 struct radeon_vm *vm);
2836int radeon_vm_bo_update(struct radeon_device *rdev,
2972int radeon_vm_bo_update(struct radeon_device *rdev,
2837 struct radeon_vm *vm,
2838 struct radeon_bo *bo,
2973 struct radeon_bo_va *bo_va,
2839 struct ttm_mem_reg *mem);
2840void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2841 struct radeon_bo *bo);
2842struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2843 struct radeon_bo *bo);
2844struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2845 struct radeon_vm *vm,
2846 struct radeon_bo *bo);
2847int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2848 struct radeon_bo_va *bo_va,
2849 uint64_t offset,
2850 uint32_t flags);
2974 struct ttm_mem_reg *mem);
2975void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2976 struct radeon_bo *bo);
2977struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2978 struct radeon_bo *bo);
2979struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2980 struct radeon_vm *vm,
2981 struct radeon_bo *bo);
2982int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2983 struct radeon_bo_va *bo_va,
2984 uint64_t offset,
2985 uint32_t flags);
2851int radeon_vm_bo_rmv(struct radeon_device *rdev,
2852 struct radeon_bo_va *bo_va);
2986void radeon_vm_bo_rmv(struct radeon_device *rdev,
2987 struct radeon_bo_va *bo_va);
2853
2854/* audio */
2855void r600_audio_update_hdmi(struct work_struct *work);
2856struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2857struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2858void r600_audio_enable(struct radeon_device *rdev,
2859 struct r600_audio_pin *pin,
2988
2989/* audio */
2990void r600_audio_update_hdmi(struct work_struct *work);
2991struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2992struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2993void r600_audio_enable(struct radeon_device *rdev,
2994 struct r600_audio_pin *pin,
2860 bool enable);
2995 u8 enable_mask);
2861void dce6_audio_enable(struct radeon_device *rdev,
2862 struct r600_audio_pin *pin,
2996void dce6_audio_enable(struct radeon_device *rdev,
2997 struct r600_audio_pin *pin,
2863 bool enable);
2998 u8 enable_mask);
2864
2865/*
2866 * R600 vram scratch functions
2867 */
2868int r600_vram_scratch_init(struct radeon_device *rdev);
2869void r600_vram_scratch_fini(struct radeon_device *rdev);
2870
2871/*

--- 70 unchanged lines hidden --- 		2999
3000/*
3001 * R600 vram scratch functions
3002 */
3003int r600_vram_scratch_init(struct radeon_device *rdev);
3004void r600_vram_scratch_fini(struct radeon_device *rdev);
3005
3006/*

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