radeon.h (8b3f6af86378d0a10ca2f1ded1da124aef13b62c) radeon.h (513bcb4655e68706594e45dfa1d4b181500110ba)
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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337/*
338 * CP & ring.
339 */
340struct radeon_ib {
341 struct list_head list;
342 unsigned long idx;
343 uint64_t gpu_addr;
344 struct radeon_fence *fence;
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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337/*
338 * CP & ring.
339 */
340struct radeon_ib {
341 struct list_head list;
342 unsigned long idx;
343 uint64_t gpu_addr;
344 struct radeon_fence *fence;
345 volatile uint32_t *ptr;
345 uint32_t *ptr;
346 uint32_t length_dw;
347};
348
349/*
350 * locking -
351 * mutex protects scheduled_ibs, ready, alloc_bm
352 */
353struct radeon_ib_pool {

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410 struct radeon_object_list lobj;
411 uint32_t handle;
412 uint32_t flags;
413};
414
415struct radeon_cs_chunk {
416 uint32_t chunk_id;
417 uint32_t length_dw;
346 uint32_t length_dw;
347};
348
349/*
350 * locking -
351 * mutex protects scheduled_ibs, ready, alloc_bm
352 */
353struct radeon_ib_pool {

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410 struct radeon_object_list lobj;
411 uint32_t handle;
412 uint32_t flags;
413};
414
415struct radeon_cs_chunk {
416 uint32_t chunk_id;
417 uint32_t length_dw;
418 int kpage_idx[2];
419 uint32_t *kpage[2];
418 uint32_t *kdata;
420 uint32_t *kdata;
421 void __user *user_ptr;
422 int last_copied_page;
423 int last_page_index;
419};
420
421struct radeon_cs_parser {
422 struct radeon_device *rdev;
423 struct drm_file *filp;
424 /* chunks */
425 unsigned nchunks;
426 struct radeon_cs_chunk *chunks;

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433 struct radeon_cs_reloc **relocs_ptr;
434 struct list_head validated;
435 /* indices of various chunks */
436 int chunk_ib_idx;
437 int chunk_relocs_idx;
438 struct radeon_ib *ib;
439 void *track;
440 unsigned family;
424};
425
426struct radeon_cs_parser {
427 struct radeon_device *rdev;
428 struct drm_file *filp;
429 /* chunks */
430 unsigned nchunks;
431 struct radeon_cs_chunk *chunks;

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438 struct radeon_cs_reloc **relocs_ptr;
439 struct list_head validated;
440 /* indices of various chunks */
441 int chunk_ib_idx;
442 int chunk_relocs_idx;
443 struct radeon_ib *ib;
444 void *track;
445 unsigned family;
446 int parser_error;
441};
442
447};
448
449extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
450extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
451
452
453static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
454{
455 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
456 u32 pg_idx, pg_offset;
457 u32 idx_value = 0;
458 int new_page;
459
460 pg_idx = (idx * 4) / PAGE_SIZE;
461 pg_offset = (idx * 4) % PAGE_SIZE;
462
463 if (ibc->kpage_idx[0] == pg_idx)
464 return ibc->kpage[0][pg_offset/4];
465 if (ibc->kpage_idx[1] == pg_idx)
466 return ibc->kpage[1][pg_offset/4];
467
468 new_page = radeon_cs_update_pages(p, pg_idx);
469 if (new_page < 0) {
470 p->parser_error = new_page;
471 return 0;
472 }
473
474 idx_value = ibc->kpage[new_page][pg_offset/4];
475 return idx_value;
476}
477
443struct radeon_cs_packet {
444 unsigned idx;
445 unsigned type;
446 unsigned reg;
447 unsigned opcode;
448 int count;
449 unsigned one_reg_wr;
450};

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534 */
535struct radeon_asic {
536 int (*init)(struct radeon_device *rdev);
537 void (*fini)(struct radeon_device *rdev);
538 int (*resume)(struct radeon_device *rdev);
539 int (*suspend)(struct radeon_device *rdev);
540 void (*errata)(struct radeon_device *rdev);
541 void (*vram_info)(struct radeon_device *rdev);
478struct radeon_cs_packet {
479 unsigned idx;
480 unsigned type;
481 unsigned reg;
482 unsigned opcode;
483 int count;
484 unsigned one_reg_wr;
485};

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569 */
570struct radeon_asic {
571 int (*init)(struct radeon_device *rdev);
572 void (*fini)(struct radeon_device *rdev);
573 int (*resume)(struct radeon_device *rdev);
574 int (*suspend)(struct radeon_device *rdev);
575 void (*errata)(struct radeon_device *rdev);
576 void (*vram_info)(struct radeon_device *rdev);
542 void (*vga_set_state)(struct radeon_device *rdev, bool state);
543 int (*gpu_reset)(struct radeon_device *rdev);
544 int (*mc_init)(struct radeon_device *rdev);
545 void (*mc_fini)(struct radeon_device *rdev);
546 int (*wb_init)(struct radeon_device *rdev);
547 void (*wb_fini)(struct radeon_device *rdev);
548 int (*gart_init)(struct radeon_device *rdev);
549 void (*gart_fini)(struct radeon_device *rdev);
550 int (*gart_enable)(struct radeon_device *rdev);

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893 */
894#define radeon_init(rdev) (rdev)->asic->init((rdev))
895#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
896#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
897#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
898#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
899#define radeon_errata(rdev) (rdev)->asic->errata((rdev))
900#define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev))
577 int (*gpu_reset)(struct radeon_device *rdev);
578 int (*mc_init)(struct radeon_device *rdev);
579 void (*mc_fini)(struct radeon_device *rdev);
580 int (*wb_init)(struct radeon_device *rdev);
581 void (*wb_fini)(struct radeon_device *rdev);
582 int (*gart_init)(struct radeon_device *rdev);
583 void (*gart_fini)(struct radeon_device *rdev);
584 int (*gart_enable)(struct radeon_device *rdev);

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927 */
928#define radeon_init(rdev) (rdev)->asic->init((rdev))
929#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
930#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
931#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
932#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
933#define radeon_errata(rdev) (rdev)->asic->errata((rdev))
934#define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev))
901#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
902#define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
903#define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev))
904#define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev))
905#define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev))
906#define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev))
907#define radeon_gpu_gart_init(rdev) (rdev)->asic->gart_init((rdev))
908#define radeon_gpu_gart_fini(rdev) (rdev)->asic->gart_fini((rdev))
909#define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev))

--- 111 unchanged lines hidden --- 		935#define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
936#define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev))
937#define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev))
938#define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev))
939#define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev))
940#define radeon_gpu_gart_init(rdev) (rdev)->asic->gart_init((rdev))
941#define radeon_gpu_gart_fini(rdev) (rdev)->asic->gart_fini((rdev))
942#define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev))

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