radeon.h (41be702a542a0d14bb0b1c16e824fa9ed27616ec) radeon.h (ebff8453d3a57a2405c4d96d9f9c4f4acc7d4d79)
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

--- 50 unchanged lines hidden (view full) ---

59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63#include <linux/atomic.h>
64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

--- 50 unchanged lines hidden (view full) ---

59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63#include <linux/atomic.h>
64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67#include <linux/interval_tree.h>
68#include <linux/hashtable.h>
69#include <linux/fence.h>
67
68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
72#include <ttm/ttm_execbuf_util.h>
73
70
71#include <ttm/ttm_bo_api.h>
72#include <ttm/ttm_bo_driver.h>
73#include <ttm/ttm_placement.h>
74#include <ttm/ttm_module.h>
75#include <ttm/ttm_execbuf_util.h>
76
77#include <drm/drm_gem.h>
78
74#include "radeon_family.h"
75#include "radeon_mode.h"
76#include "radeon_reg.h"
77
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;

--- 12 unchanged lines hidden (view full) ---

94extern int radeon_hw_i2c;
95extern int radeon_pcie_gen2;
96extern int radeon_msi;
97extern int radeon_lockup_timeout;
98extern int radeon_fastfb;
99extern int radeon_dpm;
100extern int radeon_aspm;
101extern int radeon_runtime_pm;
79#include "radeon_family.h"
80#include "radeon_mode.h"
81#include "radeon_reg.h"
82
83/*
84 * Modules parameters.
85 */
86extern int radeon_no_wb;

--- 12 unchanged lines hidden (view full) ---

99extern int radeon_hw_i2c;
100extern int radeon_pcie_gen2;
101extern int radeon_msi;
102extern int radeon_lockup_timeout;
103extern int radeon_fastfb;
104extern int radeon_dpm;
105extern int radeon_aspm;
106extern int radeon_runtime_pm;
107extern int radeon_hard_reset;
108extern int radeon_vm_size;
109extern int radeon_vm_block_size;
110extern int radeon_deep_color;
111extern int radeon_use_pflipirq;
112extern int radeon_bapm;
113extern int radeon_backlight;
102
103/*
104 * Copy from radeon_drv.h so we don't have to include both and have conflicting
105 * symbol;
106 */
107#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
108#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
109/* RADEON_IB_POOL_SIZE must be a power of 2 */
110#define RADEON_IB_POOL_SIZE 16
111#define RADEON_DEBUGFS_MAX_COMPONENTS 32
112#define RADEONFB_CONN_LIMIT 4
113#define RADEON_BIOS_NUM_SCRATCH 8
114
114
115/*
116 * Copy from radeon_drv.h so we don't have to include both and have conflicting
117 * symbol;
118 */
119#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
120#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
121/* RADEON_IB_POOL_SIZE must be a power of 2 */
122#define RADEON_IB_POOL_SIZE 16
123#define RADEON_DEBUGFS_MAX_COMPONENTS 32
124#define RADEONFB_CONN_LIMIT 4
125#define RADEON_BIOS_NUM_SCRATCH 8
126
115/* max number of rings */
116#define RADEON_NUM_RINGS 6
117
118/* fence seq are set to this number when signaled */
119#define RADEON_FENCE_SIGNALED_SEQ 0LL
120
121/* internal ring indices */
122/* r1xx+ has gfx CP ring */
127/* internal ring indices */
128/* r1xx+ has gfx CP ring */
123#define RADEON_RING_TYPE_GFX_INDEX 0
129#define RADEON_RING_TYPE_GFX_INDEX 0
124
125/* cayman has 2 compute CP rings */
130
131/* cayman has 2 compute CP rings */
126#define CAYMAN_RING_TYPE_CP1_INDEX 1
127#define CAYMAN_RING_TYPE_CP2_INDEX 2
132#define CAYMAN_RING_TYPE_CP1_INDEX 1
133#define CAYMAN_RING_TYPE_CP2_INDEX 2
128
129/* R600+ has an async dma ring */
130#define R600_RING_TYPE_DMA_INDEX 3
131/* cayman add a second async dma ring */
132#define CAYMAN_RING_TYPE_DMA1_INDEX 4
133
134/* R600+ */
134
135/* R600+ has an async dma ring */
136#define R600_RING_TYPE_DMA_INDEX 3
137/* cayman add a second async dma ring */
138#define CAYMAN_RING_TYPE_DMA1_INDEX 4
139
140/* R600+ */
135#define R600_RING_TYPE_UVD_INDEX 5
141#define R600_RING_TYPE_UVD_INDEX 5
136
142
143/* TN+ */
144#define TN_RING_TYPE_VCE1_INDEX 6
145#define TN_RING_TYPE_VCE2_INDEX 7
146
147/* max number of rings */
148#define RADEON_NUM_RINGS 8
149
150/* number of hw syncs before falling back on blocking */
151#define RADEON_NUM_SYNCS 4
152
153/* number of hw syncs before falling back on blocking */
154#define RADEON_NUM_SYNCS 4
155
137/* hardcode those limit for now */
138#define RADEON_VA_IB_OFFSET (1 << 20)
139#define RADEON_VA_RESERVED_SIZE (8 << 20)
140#define RADEON_IB_VM_MAX_SIZE (64 << 10)
141
156/* hardcode those limit for now */
157#define RADEON_VA_IB_OFFSET (1 << 20)
158#define RADEON_VA_RESERVED_SIZE (8 << 20)
159#define RADEON_IB_VM_MAX_SIZE (64 << 10)
160
161/* hard reset data */
162#define RADEON_ASIC_RESET_DATA 0x39d5e86b
163
142/* reset flags */
143#define RADEON_RESET_GFX (1 << 0)
144#define RADEON_RESET_COMPUTE (1 << 1)
145#define RADEON_RESET_DMA (1 << 2)
146#define RADEON_RESET_CP (1 << 3)
147#define RADEON_RESET_GRBM (1 << 4)
148#define RADEON_RESET_DMA1 (1 << 5)
149#define RADEON_RESET_RLC (1 << 6)

--- 97 unchanged lines hidden (view full) ---

247 uint32_t dp_extclk;
248 uint32_t max_pixel_clock;
249};
250
251/*
252 * Power management
253 */
254int radeon_pm_init(struct radeon_device *rdev);
164/* reset flags */
165#define RADEON_RESET_GFX (1 << 0)
166#define RADEON_RESET_COMPUTE (1 << 1)
167#define RADEON_RESET_DMA (1 << 2)
168#define RADEON_RESET_CP (1 << 3)
169#define RADEON_RESET_GRBM (1 << 4)
170#define RADEON_RESET_DMA1 (1 << 5)
171#define RADEON_RESET_RLC (1 << 6)

--- 97 unchanged lines hidden (view full) ---

269 uint32_t dp_extclk;
270 uint32_t max_pixel_clock;
271};
272
273/*
274 * Power management
275 */
276int radeon_pm_init(struct radeon_device *rdev);
277int radeon_pm_late_init(struct radeon_device *rdev);
255void radeon_pm_fini(struct radeon_device *rdev);
256void radeon_pm_compute_clocks(struct radeon_device *rdev);
257void radeon_pm_suspend(struct radeon_device *rdev);
258void radeon_pm_resume(struct radeon_device *rdev);
259void radeon_combios_get_power_modes(struct radeon_device *rdev);
260void radeon_atombios_get_power_modes(struct radeon_device *rdev);
261int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
262 u8 clock_type,

--- 18 unchanged lines hidden (view full) ---

281 u16 *voltage,
282 u16 leakage_idx);
283int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
284 u16 *leakage_id);
285int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
286 u16 *vddc, u16 *vddci,
287 u16 virtual_voltage_id,
288 u16 vbios_voltage_id);
278void radeon_pm_fini(struct radeon_device *rdev);
279void radeon_pm_compute_clocks(struct radeon_device *rdev);
280void radeon_pm_suspend(struct radeon_device *rdev);
281void radeon_pm_resume(struct radeon_device *rdev);
282void radeon_combios_get_power_modes(struct radeon_device *rdev);
283void radeon_atombios_get_power_modes(struct radeon_device *rdev);
284int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
285 u8 clock_type,

--- 18 unchanged lines hidden (view full) ---

304 u16 *voltage,
305 u16 leakage_idx);
306int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
307 u16 *leakage_id);
308int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
309 u16 *vddc, u16 *vddci,
310 u16 virtual_voltage_id,
311 u16 vbios_voltage_id);
312int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
313 u16 virtual_voltage_id,
314 u16 *voltage);
289int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
290 u8 voltage_type,
291 u16 nominal_voltage,
292 u16 *true_voltage);
293int radeon_atom_get_min_voltage(struct radeon_device *rdev,
294 u8 voltage_type, u16 *min_voltage);
295int radeon_atom_get_max_voltage(struct radeon_device *rdev,
296 u8 voltage_type, u16 *max_voltage);
297int radeon_atom_get_voltage_table(struct radeon_device *rdev,
298 u8 voltage_type, u8 voltage_mode,
299 struct atom_voltage_table *voltage_table);
300bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
301 u8 voltage_type, u8 voltage_mode);
315int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
316 u8 voltage_type,
317 u16 nominal_voltage,
318 u16 *true_voltage);
319int radeon_atom_get_min_voltage(struct radeon_device *rdev,
320 u8 voltage_type, u16 *min_voltage);
321int radeon_atom_get_max_voltage(struct radeon_device *rdev,
322 u8 voltage_type, u16 *max_voltage);
323int radeon_atom_get_voltage_table(struct radeon_device *rdev,
324 u8 voltage_type, u8 voltage_mode,
325 struct atom_voltage_table *voltage_table);
326bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
327 u8 voltage_type, u8 voltage_mode);
328int radeon_atom_get_svi2_info(struct radeon_device *rdev,
329 u8 voltage_type,
330 u8 *svd_gpio_id, u8 *svc_gpio_id);
302void radeon_atom_update_memory_dll(struct radeon_device *rdev,
303 u32 mem_clock);
304void radeon_atom_set_ac_timing(struct radeon_device *rdev,
305 u32 mem_clock);
306int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
307 u8 module_index,
308 struct atom_mc_reg_table *reg_table);
309int radeon_atom_get_memory_info(struct radeon_device *rdev,

--- 7 unchanged lines hidden (view full) ---

317extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
318 unsigned *bankh, unsigned *mtaspect,
319 unsigned *tile_split);
320
321/*
322 * Fences.
323 */
324struct radeon_fence_driver {
331void radeon_atom_update_memory_dll(struct radeon_device *rdev,
332 u32 mem_clock);
333void radeon_atom_set_ac_timing(struct radeon_device *rdev,
334 u32 mem_clock);
335int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
336 u8 module_index,
337 struct atom_mc_reg_table *reg_table);
338int radeon_atom_get_memory_info(struct radeon_device *rdev,

--- 7 unchanged lines hidden (view full) ---

346extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
347 unsigned *bankh, unsigned *mtaspect,
348 unsigned *tile_split);
349
350/*
351 * Fences.
352 */
353struct radeon_fence_driver {
354 struct radeon_device *rdev;
325 uint32_t scratch_reg;
326 uint64_t gpu_addr;
327 volatile uint32_t *cpu_addr;
328 /* sync_seq is protected by ring emission lock */
329 uint64_t sync_seq[RADEON_NUM_RINGS];
330 atomic64_t last_seq;
355 uint32_t scratch_reg;
356 uint64_t gpu_addr;
357 volatile uint32_t *cpu_addr;
358 /* sync_seq is protected by ring emission lock */
359 uint64_t sync_seq[RADEON_NUM_RINGS];
360 atomic64_t last_seq;
331 bool initialized;
361 bool initialized, delayed_irq;
362 struct delayed_work lockup_work;
332};
333
334struct radeon_fence {
363};
364
365struct radeon_fence {
366 struct fence base;
367
335 struct radeon_device *rdev;
368 struct radeon_device *rdev;
336 struct kref kref;
337 /* protected by radeon_fence.lock */
338 uint64_t seq;
339 /* RB, DMA, etc. */
340 unsigned ring;
369 uint64_t seq;
370 /* RB, DMA, etc. */
371 unsigned ring;
372
373 wait_queue_t fence_wake;
341};
342
343int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
344int radeon_fence_driver_init(struct radeon_device *rdev);
345void radeon_fence_driver_fini(struct radeon_device *rdev);
374};
375
376int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
377int radeon_fence_driver_init(struct radeon_device *rdev);
378void radeon_fence_driver_fini(struct radeon_device *rdev);
346void radeon_fence_driver_force_completion(struct radeon_device *rdev);
379void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
347int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
348void radeon_fence_process(struct radeon_device *rdev, int ring);
349bool radeon_fence_signaled(struct radeon_fence *fence);
350int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
380int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
381void radeon_fence_process(struct radeon_device *rdev, int ring);
382bool radeon_fence_signaled(struct radeon_fence *fence);
383int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
351int radeon_fence_wait_locked(struct radeon_fence *fence);
352int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
353int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
384int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
385int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
354int radeon_fence_wait_any(struct radeon_device *rdev,
355 struct radeon_fence **fences,
356 bool intr);
357struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
358void radeon_fence_unref(struct radeon_fence **fence);
359unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
360bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
361void radeon_fence_note_sync(struct radeon_fence *fence, int ring);

--- 46 unchanged lines hidden (view full) ---

408 * TTM.
409 */
410struct radeon_mman {
411 struct ttm_bo_global_ref bo_global_ref;
412 struct drm_global_reference mem_global_ref;
413 struct ttm_bo_device bdev;
414 bool mem_global_referenced;
415 bool initialized;
386int radeon_fence_wait_any(struct radeon_device *rdev,
387 struct radeon_fence **fences,
388 bool intr);
389struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
390void radeon_fence_unref(struct radeon_fence **fence);
391unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
392bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
393void radeon_fence_note_sync(struct radeon_fence *fence, int ring);

--- 46 unchanged lines hidden (view full) ---

440 * TTM.
441 */
442struct radeon_mman {
443 struct ttm_bo_global_ref bo_global_ref;
444 struct drm_global_reference mem_global_ref;
445 struct ttm_bo_device bdev;
446 bool mem_global_referenced;
447 bool initialized;
448
449#if defined(CONFIG_DEBUG_FS)
450 struct dentry *vram;
451 struct dentry *gtt;
452#endif
416};
417
418/* bo virtual address in a specific vm */
419struct radeon_bo_va {
420 /* protected by bo being reserved */
421 struct list_head bo_list;
453};
454
455/* bo virtual address in a specific vm */
456struct radeon_bo_va {
457 /* protected by bo being reserved */
458 struct list_head bo_list;
422 uint64_t soffset;
423 uint64_t eoffset;
424 uint32_t flags;
459 uint32_t flags;
425 bool valid;
460 uint64_t addr;
426 unsigned ref_count;
427
428 /* protected by vm mutex */
461 unsigned ref_count;
462
463 /* protected by vm mutex */
429 struct list_head vm_list;
464 struct interval_tree_node it;
465 struct list_head vm_status;
430
431 /* constant after initialization */
432 struct radeon_vm *vm;
433 struct radeon_bo *bo;
434};
435
436struct radeon_bo {
437 /* Protected by gem.mutex */
438 struct list_head list;
439 /* Protected by tbo.reserved */
466
467 /* constant after initialization */
468 struct radeon_vm *vm;
469 struct radeon_bo *bo;
470};
471
472struct radeon_bo {
473 /* Protected by gem.mutex */
474 struct list_head list;
475 /* Protected by tbo.reserved */
440 u32 placements[3];
476 u32 initial_domain;
477 struct ttm_place placements[4];
441 struct ttm_placement placement;
442 struct ttm_buffer_object tbo;
443 struct ttm_bo_kmap_obj kmap;
478 struct ttm_placement placement;
479 struct ttm_buffer_object tbo;
480 struct ttm_bo_kmap_obj kmap;
481 u32 flags;
444 unsigned pin_count;
445 void *kptr;
446 u32 tiling_flags;
447 u32 pitch;
448 int surface_reg;
449 /* list of all virtual address to which this bo
450 * is associated to
451 */
452 struct list_head va;
453 /* Constant after initialization */
454 struct radeon_device *rdev;
455 struct drm_gem_object gem_base;
456
457 struct ttm_bo_kmap_obj dma_buf_vmap;
458 pid_t pid;
482 unsigned pin_count;
483 void *kptr;
484 u32 tiling_flags;
485 u32 pitch;
486 int surface_reg;
487 /* list of all virtual address to which this bo
488 * is associated to
489 */
490 struct list_head va;
491 /* Constant after initialization */
492 struct radeon_device *rdev;
493 struct drm_gem_object gem_base;
494
495 struct ttm_bo_kmap_obj dma_buf_vmap;
496 pid_t pid;
497
498 struct radeon_mn *mn;
499 struct interval_tree_node mn_it;
459};
460#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
461
500};
501#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
502
462struct radeon_bo_list {
463 struct ttm_validate_buffer tv;
464 struct radeon_bo *bo;
465 uint64_t gpu_offset;
466 bool written;
467 unsigned domain;
468 unsigned alt_domain;
469 u32 tiling_flags;
470};
471
472int radeon_gem_debugfs_init(struct radeon_device *rdev);
473
474/* sub-allocation manager, it has to be protected by another lock.
475 * By conception this is an helper for other part of the driver
476 * like the indirect buffer or semaphore, which both have their
477 * locking.
478 *
479 * Principe is simple, we keep a list of sub allocation in offset

--- 44 unchanged lines hidden (view full) ---

524 */
525struct radeon_gem {
526 struct mutex mutex;
527 struct list_head objects;
528};
529
530int radeon_gem_init(struct radeon_device *rdev);
531void radeon_gem_fini(struct radeon_device *rdev);
503int radeon_gem_debugfs_init(struct radeon_device *rdev);
504
505/* sub-allocation manager, it has to be protected by another lock.
506 * By conception this is an helper for other part of the driver
507 * like the indirect buffer or semaphore, which both have their
508 * locking.
509 *
510 * Principe is simple, we keep a list of sub allocation in offset

--- 44 unchanged lines hidden (view full) ---

555 */
556struct radeon_gem {
557 struct mutex mutex;
558 struct list_head objects;
559};
560
561int radeon_gem_init(struct radeon_device *rdev);
562void radeon_gem_fini(struct radeon_device *rdev);
532int radeon_gem_object_create(struct radeon_device *rdev, int size,
563int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
533 int alignment, int initial_domain,
564 int alignment, int initial_domain,
534 bool discardable, bool kernel,
565 u32 flags, bool kernel,
535 struct drm_gem_object **obj);
536
537int radeon_mode_dumb_create(struct drm_file *file_priv,
538 struct drm_device *dev,
539 struct drm_mode_create_dumb *args);
540int radeon_mode_dumb_mmap(struct drm_file *filp,
541 struct drm_device *dev,
542 uint32_t handle, uint64_t *offset_p);
543
544/*
545 * Semaphores.
546 */
566 struct drm_gem_object **obj);
567
568int radeon_mode_dumb_create(struct drm_file *file_priv,
569 struct drm_device *dev,
570 struct drm_mode_create_dumb *args);
571int radeon_mode_dumb_mmap(struct drm_file *filp,
572 struct drm_device *dev,
573 uint32_t handle, uint64_t *offset_p);
574
575/*
576 * Semaphores.
577 */
547/* everything here is constant */
548struct radeon_semaphore {
549 struct radeon_sa_bo *sa_bo;
550 signed waiters;
551 uint64_t gpu_addr;
552 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
553};
554
555int radeon_semaphore_create(struct radeon_device *rdev,
556 struct radeon_semaphore **semaphore);
557bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
558 struct radeon_semaphore *semaphore);
559bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
560 struct radeon_semaphore *semaphore);
578struct radeon_semaphore {
579 struct radeon_sa_bo *sa_bo;
580 signed waiters;
581 uint64_t gpu_addr;
582 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
583};
584
585int radeon_semaphore_create(struct radeon_device *rdev,
586 struct radeon_semaphore **semaphore);
587bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
588 struct radeon_semaphore *semaphore);
589bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
590 struct radeon_semaphore *semaphore);
561void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore,
562 struct radeon_fence *fence);
591void radeon_semaphore_sync_fence(struct radeon_semaphore *semaphore,
592 struct radeon_fence *fence);
593int radeon_semaphore_sync_resv(struct radeon_device *rdev,
594 struct radeon_semaphore *semaphore,
595 struct reservation_object *resv,
596 bool shared);
563int radeon_semaphore_sync_rings(struct radeon_device *rdev,
564 struct radeon_semaphore *semaphore,
565 int waiting_ring);
566void radeon_semaphore_free(struct radeon_device *rdev,
567 struct radeon_semaphore **semaphore,
568 struct radeon_fence *fence);
569
570/*
571 * GART structures, functions & helpers
572 */
573struct radeon_mc;
574
575#define RADEON_GPU_PAGE_SIZE 4096
576#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
577#define RADEON_GPU_PAGE_SHIFT 12
578#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
579
597int radeon_semaphore_sync_rings(struct radeon_device *rdev,
598 struct radeon_semaphore *semaphore,
599 int waiting_ring);
600void radeon_semaphore_free(struct radeon_device *rdev,
601 struct radeon_semaphore **semaphore,
602 struct radeon_fence *fence);
603
604/*
605 * GART structures, functions & helpers
606 */
607struct radeon_mc;
608
609#define RADEON_GPU_PAGE_SIZE 4096
610#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
611#define RADEON_GPU_PAGE_SHIFT 12
612#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
613
614#define RADEON_GART_PAGE_DUMMY 0
615#define RADEON_GART_PAGE_VALID (1 << 0)
616#define RADEON_GART_PAGE_READ (1 << 1)
617#define RADEON_GART_PAGE_WRITE (1 << 2)
618#define RADEON_GART_PAGE_SNOOP (1 << 3)
619
580struct radeon_gart {
581 dma_addr_t table_addr;
582 struct radeon_bo *robj;
583 void *ptr;
584 unsigned num_gpu_pages;
585 unsigned num_cpu_pages;
586 unsigned table_size;
587 struct page **pages;

--- 8 unchanged lines hidden (view full) ---

596int radeon_gart_table_vram_pin(struct radeon_device *rdev);
597void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
598int radeon_gart_init(struct radeon_device *rdev);
599void radeon_gart_fini(struct radeon_device *rdev);
600void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
601 int pages);
602int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
603 int pages, struct page **pagelist,
620struct radeon_gart {
621 dma_addr_t table_addr;
622 struct radeon_bo *robj;
623 void *ptr;
624 unsigned num_gpu_pages;
625 unsigned num_cpu_pages;
626 unsigned table_size;
627 struct page **pages;

--- 8 unchanged lines hidden (view full) ---

636int radeon_gart_table_vram_pin(struct radeon_device *rdev);
637void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
638int radeon_gart_init(struct radeon_device *rdev);
639void radeon_gart_fini(struct radeon_device *rdev);
640void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
641 int pages);
642int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
643 int pages, struct page **pagelist,
604 dma_addr_t *dma_addr);
605void radeon_gart_restore(struct radeon_device *rdev);
644 dma_addr_t *dma_addr, uint32_t flags);
606
607
608/*
609 * GPU MC structures, functions & helpers
610 */
611struct radeon_mc {
612 resource_size_t aper_size;
613 resource_size_t aper_base;

--- 43 unchanged lines hidden (view full) ---

657 resource_size_t size;
658 u32 __iomem *ptr;
659 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
660 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
661};
662
663int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
664void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
645
646
647/*
648 * GPU MC structures, functions & helpers
649 */
650struct radeon_mc {
651 resource_size_t aper_size;
652 resource_size_t aper_base;

--- 43 unchanged lines hidden (view full) ---

696 resource_size_t size;
697 u32 __iomem *ptr;
698 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
699 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
700};
701
702int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
703void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
704void radeon_doorbell_get_kfd_info(struct radeon_device *rdev,
705 phys_addr_t *aperture_base,
706 size_t *aperture_size,
707 size_t *start_offset);
665
666/*
667 * IRQS.
668 */
669
708
709/*
710 * IRQS.
711 */
712
670struct radeon_unpin_work {
671 struct work_struct work;
672 struct radeon_device *rdev;
673 int crtc_id;
674 struct radeon_fence *fence;
713struct radeon_flip_work {
714 struct work_struct flip_work;
715 struct work_struct unpin_work;
716 struct radeon_device *rdev;
717 int crtc_id;
718 uint64_t base;
675 struct drm_pending_vblank_event *event;
719 struct drm_pending_vblank_event *event;
676 struct radeon_bo *old_rbo;
677 u64 new_crtc_base;
720 struct radeon_bo *old_rbo;
721 struct fence *fence;
678};
679
680struct r500_irq_stat_regs {
681 u32 disp_int;
682 u32 hdmi0_status;
683};
684
685struct r600_irq_stat_regs {

--- 30 unchanged lines hidden (view full) ---

716struct cik_irq_stat_regs {
717 u32 disp_int;
718 u32 disp_int_cont;
719 u32 disp_int_cont2;
720 u32 disp_int_cont3;
721 u32 disp_int_cont4;
722 u32 disp_int_cont5;
723 u32 disp_int_cont6;
722};
723
724struct r500_irq_stat_regs {
725 u32 disp_int;
726 u32 hdmi0_status;
727};
728
729struct r600_irq_stat_regs {

--- 30 unchanged lines hidden (view full) ---

760struct cik_irq_stat_regs {
761 u32 disp_int;
762 u32 disp_int_cont;
763 u32 disp_int_cont2;
764 u32 disp_int_cont3;
765 u32 disp_int_cont4;
766 u32 disp_int_cont5;
767 u32 disp_int_cont6;
768 u32 d1grph_int;
769 u32 d2grph_int;
770 u32 d3grph_int;
771 u32 d4grph_int;
772 u32 d5grph_int;
773 u32 d6grph_int;
724};
725
726union radeon_irq_stat_regs {
727 struct r500_irq_stat_regs r500;
728 struct r600_irq_stat_regs r600;
729 struct evergreen_irq_stat_regs evergreen;
730 struct cik_irq_stat_regs cik;
731};
732
774};
775
776union radeon_irq_stat_regs {
777 struct r500_irq_stat_regs r500;
778 struct r600_irq_stat_regs r600;
779 struct evergreen_irq_stat_regs evergreen;
780 struct cik_irq_stat_regs cik;
781};
782
733#define RADEON_MAX_HPD_PINS 6
734#define RADEON_MAX_CRTCS 6
735#define RADEON_MAX_AFMT_BLOCKS 7
736
737struct radeon_irq {
738 bool installed;
739 spinlock_t lock;
740 atomic_t ring_int[RADEON_NUM_RINGS];
741 bool crtc_vblank_int[RADEON_MAX_CRTCS];
742 atomic_t pflip[RADEON_MAX_CRTCS];
743 wait_queue_head_t vblank_queue;
744 bool hpd[RADEON_MAX_HPD_PINS];
745 bool afmt[RADEON_MAX_AFMT_BLOCKS];
746 union radeon_irq_stat_regs stat_regs;
747 bool dpm_thermal;
748};
749
750int radeon_irq_kms_init(struct radeon_device *rdev);
751void radeon_irq_kms_fini(struct radeon_device *rdev);
752void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
783struct radeon_irq {
784 bool installed;
785 spinlock_t lock;
786 atomic_t ring_int[RADEON_NUM_RINGS];
787 bool crtc_vblank_int[RADEON_MAX_CRTCS];
788 atomic_t pflip[RADEON_MAX_CRTCS];
789 wait_queue_head_t vblank_queue;
790 bool hpd[RADEON_MAX_HPD_PINS];
791 bool afmt[RADEON_MAX_AFMT_BLOCKS];
792 union radeon_irq_stat_regs stat_regs;
793 bool dpm_thermal;
794};
795
796int radeon_irq_kms_init(struct radeon_device *rdev);
797void radeon_irq_kms_fini(struct radeon_device *rdev);
798void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
799bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
753void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
754void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
755void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
756void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
757void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
758void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
759void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
760

--- 11 unchanged lines hidden (view full) ---

772 struct radeon_vm *vm;
773 bool is_const_ib;
774 struct radeon_semaphore *semaphore;
775};
776
777struct radeon_ring {
778 struct radeon_bo *ring_obj;
779 volatile uint32_t *ring;
800void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
801void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
802void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
803void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
804void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
805void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
806void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
807

--- 11 unchanged lines hidden (view full) ---

819 struct radeon_vm *vm;
820 bool is_const_ib;
821 struct radeon_semaphore *semaphore;
822};
823
824struct radeon_ring {
825 struct radeon_bo *ring_obj;
826 volatile uint32_t *ring;
780 unsigned rptr;
781 unsigned rptr_offs;
827 unsigned rptr_offs;
782 unsigned rptr_reg;
783 unsigned rptr_save_reg;
784 u64 next_rptr_gpu_addr;
785 volatile u32 *next_rptr_cpu_addr;
786 unsigned wptr;
787 unsigned wptr_old;
828 unsigned rptr_save_reg;
829 u64 next_rptr_gpu_addr;
830 volatile u32 *next_rptr_cpu_addr;
831 unsigned wptr;
832 unsigned wptr_old;
788 unsigned wptr_reg;
789 unsigned ring_size;
790 unsigned ring_free_dw;
791 int count_dw;
833 unsigned ring_size;
834 unsigned ring_free_dw;
835 int count_dw;
792 unsigned long last_activity;
793 unsigned last_rptr;
836 atomic_t last_rptr;
837 atomic64_t last_activity;
794 uint64_t gpu_addr;
795 uint32_t align_mask;
796 uint32_t ptr_mask;
797 bool ready;
798 u32 nop;
799 u32 idx;
800 u64 last_semaphore_signal_addr;
801 u64 last_semaphore_wait_addr;

--- 16 unchanged lines hidden (view full) ---

818
819/*
820 * VM
821 */
822
823/* maximum number of VMIDs */
824#define RADEON_NUM_VM 16
825
838 uint64_t gpu_addr;
839 uint32_t align_mask;
840 uint32_t ptr_mask;
841 bool ready;
842 u32 nop;
843 u32 idx;
844 u64 last_semaphore_signal_addr;
845 u64 last_semaphore_wait_addr;

--- 16 unchanged lines hidden (view full) ---

862
863/*
864 * VM
865 */
866
867/* maximum number of VMIDs */
868#define RADEON_NUM_VM 16
869
826/* defines number of bits in page table versus page directory,
827 * a page is 4KB so we have 12 bits offset, 9 bits in the page
828 * table and the remaining 19 bits are in the page directory */
829#define RADEON_VM_BLOCK_SIZE 9
830
831/* number of entries in page table */
870/* number of entries in page table */
832#define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
871#define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
833
834/* PTBs (Page Table Blocks) need to be aligned to 32K */
835#define RADEON_VM_PTB_ALIGN_SIZE 32768
836#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
837#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
838
839#define R600_PTE_VALID (1 << 0)
840#define R600_PTE_SYSTEM (1 << 1)
841#define R600_PTE_SNOOPED (1 << 2)
842#define R600_PTE_READABLE (1 << 5)
843#define R600_PTE_WRITEABLE (1 << 6)
844
872
873/* PTBs (Page Table Blocks) need to be aligned to 32K */
874#define RADEON_VM_PTB_ALIGN_SIZE 32768
875#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
876#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
877
878#define R600_PTE_VALID (1 << 0)
879#define R600_PTE_SYSTEM (1 << 1)
880#define R600_PTE_SNOOPED (1 << 2)
881#define R600_PTE_READABLE (1 << 5)
882#define R600_PTE_WRITEABLE (1 << 6)
883
884/* PTE (Page Table Entry) fragment field for different page sizes */
885#define R600_PTE_FRAG_4KB (0 << 7)
886#define R600_PTE_FRAG_64KB (4 << 7)
887#define R600_PTE_FRAG_256KB (6 << 7)
888
889/* flags needed to be set so we can copy directly from the GART table */
890#define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
891 R600_PTE_SYSTEM | R600_PTE_VALID )
892
893struct radeon_vm_pt {
894 struct radeon_bo *bo;
895 uint64_t addr;
896};
897
845struct radeon_vm {
898struct radeon_vm {
846 struct list_head list;
847 struct list_head va;
899 struct rb_root va;
848 unsigned id;
849
900 unsigned id;
901
902 /* BOs moved, but not yet updated in the PT */
903 struct list_head invalidated;
904
905 /* BOs freed, but not yet updated in the PT */
906 struct list_head freed;
907
850 /* contains the page directory */
908 /* contains the page directory */
851 struct radeon_sa_bo *page_directory;
909 struct radeon_bo *page_directory;
852 uint64_t pd_gpu_addr;
910 uint64_t pd_gpu_addr;
911 unsigned max_pde_used;
853
854 /* array of page tables, one for each page directory entry */
912
913 /* array of page tables, one for each page directory entry */
855 struct radeon_sa_bo **page_tables;
914 struct radeon_vm_pt *page_tables;
856
915
916 struct radeon_bo_va *ib_bo_va;
917
857 struct mutex mutex;
858 /* last fence for cs using this vm */
859 struct radeon_fence *fence;
860 /* last flush or NULL if we still need to flush */
861 struct radeon_fence *last_flush;
918 struct mutex mutex;
919 /* last fence for cs using this vm */
920 struct radeon_fence *fence;
921 /* last flush or NULL if we still need to flush */
922 struct radeon_fence *last_flush;
923 /* last use of vmid */
924 struct radeon_fence *last_id_use;
862};
863
864struct radeon_vm_manager {
925};
926
927struct radeon_vm_manager {
865 struct mutex lock;
866 struct list_head lru_vm;
867 struct radeon_fence *active[RADEON_NUM_VM];
928 struct radeon_fence *active[RADEON_NUM_VM];
868 struct radeon_sa_manager sa_manager;
869 uint32_t max_pfn;
870 /* number of VMIDs */
871 unsigned nvm;
872 /* vram base address for page table entry */
873 u64 vram_base_offset;
874 /* is vm enabled? */
875 bool enabled;
929 uint32_t max_pfn;
930 /* number of VMIDs */
931 unsigned nvm;
932 /* vram base address for page table entry */
933 u64 vram_base_offset;
934 /* is vm enabled? */
935 bool enabled;
936 /* for hw to save the PD addr on suspend/resume */
937 uint32_t saved_table_addr[RADEON_NUM_VM];
876};
877
878/*
879 * file private structure
880 */
881struct radeon_fpriv {
882 struct radeon_vm vm;
883};

--- 37 unchanged lines hidden (view full) ---

921 u32 cp_table_size;
922};
923
924int radeon_ib_get(struct radeon_device *rdev, int ring,
925 struct radeon_ib *ib, struct radeon_vm *vm,
926 unsigned size);
927void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
928int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
938};
939
940/*
941 * file private structure
942 */
943struct radeon_fpriv {
944 struct radeon_vm vm;
945};

--- 37 unchanged lines hidden (view full) ---

983 u32 cp_table_size;
984};
985
986int radeon_ib_get(struct radeon_device *rdev, int ring,
987 struct radeon_ib *ib, struct radeon_vm *vm,
988 unsigned size);
989void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
990int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
929 struct radeon_ib *const_ib);
991 struct radeon_ib *const_ib, bool hdp_flush);
930int radeon_ib_pool_init(struct radeon_device *rdev);
931void radeon_ib_pool_fini(struct radeon_device *rdev);
932int radeon_ib_ring_tests(struct radeon_device *rdev);
933/* Ring access between begin & end cannot sleep */
934bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
935 struct radeon_ring *ring);
936void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
937int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
938int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
992int radeon_ib_pool_init(struct radeon_device *rdev);
993void radeon_ib_pool_fini(struct radeon_device *rdev);
994int radeon_ib_ring_tests(struct radeon_device *rdev);
995/* Ring access between begin & end cannot sleep */
996bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
997 struct radeon_ring *ring);
998void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
999int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1000int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
939void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
940void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
1001void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1002 bool hdp_flush);
1003void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1004 bool hdp_flush);
941void radeon_ring_undo(struct radeon_ring *ring);
942void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
943int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
1005void radeon_ring_undo(struct radeon_ring *ring);
1006void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
1007int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
944void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
945void radeon_ring_lockup_update(struct radeon_ring *ring);
1008void radeon_ring_lockup_update(struct radeon_device *rdev,
1009 struct radeon_ring *ring);
946bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
947unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
948 uint32_t **data);
949int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
950 unsigned size, uint32_t *data);
951int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
1010bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
1011unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
1012 uint32_t **data);
1013int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
1014 unsigned size, uint32_t *data);
1015int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
952 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, u32 nop);
1016 unsigned rptr_offs, u32 nop);
953void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
954
955
956/* r600 async dma */
957void r600_dma_stop(struct radeon_device *rdev);
958int r600_dma_resume(struct radeon_device *rdev);
959void r600_dma_fini(struct radeon_device *rdev);
960
961void cayman_dma_stop(struct radeon_device *rdev);
962int cayman_dma_resume(struct radeon_device *rdev);
963void cayman_dma_fini(struct radeon_device *rdev);
964
965/*
966 * CS.
967 */
968struct radeon_cs_reloc {
969 struct drm_gem_object *gobj;
970 struct radeon_bo *robj;
1017void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
1018
1019
1020/* r600 async dma */
1021void r600_dma_stop(struct radeon_device *rdev);
1022int r600_dma_resume(struct radeon_device *rdev);
1023void r600_dma_fini(struct radeon_device *rdev);
1024
1025void cayman_dma_stop(struct radeon_device *rdev);
1026int cayman_dma_resume(struct radeon_device *rdev);
1027void cayman_dma_fini(struct radeon_device *rdev);
1028
1029/*
1030 * CS.
1031 */
1032struct radeon_cs_reloc {
1033 struct drm_gem_object *gobj;
1034 struct radeon_bo *robj;
971 struct radeon_bo_list lobj;
1035 struct ttm_validate_buffer tv;
1036 uint64_t gpu_offset;
1037 unsigned prefered_domains;
1038 unsigned allowed_domains;
1039 uint32_t tiling_flags;
972 uint32_t handle;
1040 uint32_t handle;
973 uint32_t flags;
974};
975
976struct radeon_cs_chunk {
977 uint32_t chunk_id;
978 uint32_t length_dw;
979 uint32_t *kdata;
980 void __user *user_ptr;
981};

--- 7 unchanged lines hidden (view full) ---

989 struct radeon_cs_chunk *chunks;
990 uint64_t *chunks_array;
991 /* IB */
992 unsigned idx;
993 /* relocations */
994 unsigned nrelocs;
995 struct radeon_cs_reloc *relocs;
996 struct radeon_cs_reloc **relocs_ptr;
1041};
1042
1043struct radeon_cs_chunk {
1044 uint32_t chunk_id;
1045 uint32_t length_dw;
1046 uint32_t *kdata;
1047 void __user *user_ptr;
1048};

--- 7 unchanged lines hidden (view full) ---

1056 struct radeon_cs_chunk *chunks;
1057 uint64_t *chunks_array;
1058 /* IB */
1059 unsigned idx;
1060 /* relocations */
1061 unsigned nrelocs;
1062 struct radeon_cs_reloc *relocs;
1063 struct radeon_cs_reloc **relocs_ptr;
1064 struct radeon_cs_reloc *vm_bos;
997 struct list_head validated;
998 unsigned dma_reloc_idx;
999 /* indices of various chunks */
1000 int chunk_ib_idx;
1001 int chunk_relocs_idx;
1002 int chunk_flags_idx;
1003 int chunk_const_ib_idx;
1004 struct radeon_ib ib;

--- 59 unchanged lines hidden (view full) ---

1064#define RADEON_WB_CP1_RPTR_OFFSET 1280
1065#define RADEON_WB_CP2_RPTR_OFFSET 1536
1066#define R600_WB_DMA_RPTR_OFFSET 1792
1067#define R600_WB_IH_WPTR_OFFSET 2048
1068#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1069#define R600_WB_EVENT_OFFSET 3072
1070#define CIK_WB_CP1_WPTR_OFFSET 3328
1071#define CIK_WB_CP2_WPTR_OFFSET 3584
1065 struct list_head validated;
1066 unsigned dma_reloc_idx;
1067 /* indices of various chunks */
1068 int chunk_ib_idx;
1069 int chunk_relocs_idx;
1070 int chunk_flags_idx;
1071 int chunk_const_ib_idx;
1072 struct radeon_ib ib;

--- 59 unchanged lines hidden (view full) ---

1132#define RADEON_WB_CP1_RPTR_OFFSET 1280
1133#define RADEON_WB_CP2_RPTR_OFFSET 1536
1134#define R600_WB_DMA_RPTR_OFFSET 1792
1135#define R600_WB_IH_WPTR_OFFSET 2048
1136#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1137#define R600_WB_EVENT_OFFSET 3072
1138#define CIK_WB_CP1_WPTR_OFFSET 3328
1139#define CIK_WB_CP2_WPTR_OFFSET 3584
1140#define R600_WB_DMA_RING_TEST_OFFSET 3588
1141#define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
1072
1073/**
1074 * struct radeon_pm - power management datas
1075 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1076 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1077 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1078 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1079 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)

--- 158 unchanged lines hidden (view full) ---

1238enum radeon_dpm_event_src {
1239 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1240 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1241 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1242 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1243 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1244};
1245
1142
1143/**
1144 * struct radeon_pm - power management datas
1145 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1146 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1147 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1148 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1149 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)

--- 158 unchanged lines hidden (view full) ---

1308enum radeon_dpm_event_src {
1309 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1310 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1311 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1312 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1313 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1314};
1315
1316#define RADEON_MAX_VCE_LEVELS 6
1317
1318enum radeon_vce_level {
1319 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1320 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1321 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1322 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1323 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1324 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1325};
1326
1246struct radeon_ps {
1247 u32 caps; /* vbios flags */
1248 u32 class; /* vbios flags */
1249 u32 class2; /* vbios flags */
1250 /* UVD clocks */
1251 u32 vclk;
1252 u32 dclk;
1253 /* VCE clocks */
1254 u32 evclk;
1255 u32 ecclk;
1327struct radeon_ps {
1328 u32 caps; /* vbios flags */
1329 u32 class; /* vbios flags */
1330 u32 class2; /* vbios flags */
1331 /* UVD clocks */
1332 u32 vclk;
1333 u32 dclk;
1334 /* VCE clocks */
1335 u32 evclk;
1336 u32 ecclk;
1337 bool vce_active;
1338 enum radeon_vce_level vce_level;
1256 /* asic priv */
1257 void *ps_priv;
1258};
1259
1260struct radeon_dpm_thermal {
1261 /* thermal interrupt work */
1262 struct work_struct work;
1263 /* low temperature threshold */

--- 158 unchanged lines hidden (view full) ---

1422};
1423
1424enum radeon_dpm_forced_level {
1425 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1426 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1427 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1428};
1429
1339 /* asic priv */
1340 void *ps_priv;
1341};
1342
1343struct radeon_dpm_thermal {
1344 /* thermal interrupt work */
1345 struct work_struct work;
1346 /* low temperature threshold */

--- 158 unchanged lines hidden (view full) ---

1505};
1506
1507enum radeon_dpm_forced_level {
1508 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1509 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1510 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1511};
1512
1513struct radeon_vce_state {
1514 /* vce clocks */
1515 u32 evclk;
1516 u32 ecclk;
1517 /* gpu clocks */
1518 u32 sclk;
1519 u32 mclk;
1520 u8 clk_idx;
1521 u8 pstate;
1522};
1523
1430struct radeon_dpm {
1431 struct radeon_ps *ps;
1432 /* number of valid power states */
1433 int num_ps;
1434 /* current power state that is active */
1435 struct radeon_ps *current_ps;
1436 /* requested power state */
1437 struct radeon_ps *requested_ps;
1438 /* boot up power state */
1439 struct radeon_ps *boot_ps;
1440 /* default uvd power state */
1441 struct radeon_ps *uvd_ps;
1524struct radeon_dpm {
1525 struct radeon_ps *ps;
1526 /* number of valid power states */
1527 int num_ps;
1528 /* current power state that is active */
1529 struct radeon_ps *current_ps;
1530 /* requested power state */
1531 struct radeon_ps *requested_ps;
1532 /* boot up power state */
1533 struct radeon_ps *boot_ps;
1534 /* default uvd power state */
1535 struct radeon_ps *uvd_ps;
1536 /* vce requirements */
1537 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1538 enum radeon_vce_level vce_level;
1442 enum radeon_pm_state_type state;
1443 enum radeon_pm_state_type user_state;
1444 u32 platform_caps;
1445 u32 voltage_response_time;
1446 u32 backbias_response_time;
1447 void *priv;
1448 u32 new_active_crtcs;
1449 int new_active_crtc_count;

--- 9 unchanged lines hidden (view full) ---

1459 u16 tdp_od_limit;
1460 u32 tdp_adjustment;
1461 u16 load_line_slope;
1462 bool power_control;
1463 bool ac_power;
1464 /* special states active */
1465 bool thermal_active;
1466 bool uvd_active;
1539 enum radeon_pm_state_type state;
1540 enum radeon_pm_state_type user_state;
1541 u32 platform_caps;
1542 u32 voltage_response_time;
1543 u32 backbias_response_time;
1544 void *priv;
1545 u32 new_active_crtcs;
1546 int new_active_crtc_count;

--- 9 unchanged lines hidden (view full) ---

1556 u16 tdp_od_limit;
1557 u32 tdp_adjustment;
1558 u16 load_line_slope;
1559 bool power_control;
1560 bool ac_power;
1561 /* special states active */
1562 bool thermal_active;
1563 bool uvd_active;
1564 bool vce_active;
1467 /* thermal handling */
1468 struct radeon_dpm_thermal thermal;
1469 /* forced levels */
1470 enum radeon_dpm_forced_level forced_level;
1471 /* track UVD streams */
1472 unsigned sd;
1473 unsigned hd;
1474};
1475
1476void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1565 /* thermal handling */
1566 struct radeon_dpm_thermal thermal;
1567 /* forced levels */
1568 enum radeon_dpm_forced_level forced_level;
1569 /* track UVD streams */
1570 unsigned sd;
1571 unsigned hd;
1572};
1573
1574void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1575void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1477
1478struct radeon_pm {
1479 struct mutex mutex;
1480 /* write locked while reprogramming mclk */
1481 struct rw_semaphore mclk_lock;
1482 u32 active_crtcs;
1483 int active_crtc_count;
1484 int req_vblank;

--- 38 unchanged lines hidden (view full) ---

1523 bool dynpm_can_downclock;
1524 /* profile-based power management */
1525 enum radeon_pm_profile_type profile;
1526 int profile_index;
1527 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1528 /* internal thermal controller on rv6xx+ */
1529 enum radeon_int_thermal_type int_thermal_type;
1530 struct device *int_hwmon_dev;
1576
1577struct radeon_pm {
1578 struct mutex mutex;
1579 /* write locked while reprogramming mclk */
1580 struct rw_semaphore mclk_lock;
1581 u32 active_crtcs;
1582 int active_crtc_count;
1583 int req_vblank;

--- 38 unchanged lines hidden (view full) ---

1622 bool dynpm_can_downclock;
1623 /* profile-based power management */
1624 enum radeon_pm_profile_type profile;
1625 int profile_index;
1626 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1627 /* internal thermal controller on rv6xx+ */
1628 enum radeon_int_thermal_type int_thermal_type;
1629 struct device *int_hwmon_dev;
1630 /* fan control parameters */
1631 bool no_fan;
1632 u8 fan_pulses_per_revolution;
1633 u8 fan_min_rpm;
1634 u8 fan_max_rpm;
1531 /* dpm */
1532 bool dpm_enabled;
1533 struct radeon_dpm dpm;
1534};
1535
1536int radeon_pm_get_type_index(struct radeon_device *rdev,
1537 enum radeon_pm_state_type ps_type,
1538 int instance);

--- 18 unchanged lines hidden (view full) ---

1557int radeon_uvd_init(struct radeon_device *rdev);
1558void radeon_uvd_fini(struct radeon_device *rdev);
1559int radeon_uvd_suspend(struct radeon_device *rdev);
1560int radeon_uvd_resume(struct radeon_device *rdev);
1561int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1562 uint32_t handle, struct radeon_fence **fence);
1563int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1564 uint32_t handle, struct radeon_fence **fence);
1635 /* dpm */
1636 bool dpm_enabled;
1637 struct radeon_dpm dpm;
1638};
1639
1640int radeon_pm_get_type_index(struct radeon_device *rdev,
1641 enum radeon_pm_state_type ps_type,
1642 int instance);

--- 18 unchanged lines hidden (view full) ---

1661int radeon_uvd_init(struct radeon_device *rdev);
1662void radeon_uvd_fini(struct radeon_device *rdev);
1663int radeon_uvd_suspend(struct radeon_device *rdev);
1664int radeon_uvd_resume(struct radeon_device *rdev);
1665int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1666 uint32_t handle, struct radeon_fence **fence);
1667int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1668 uint32_t handle, struct radeon_fence **fence);
1565void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1669void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1670 uint32_t allowed_domains);
1566void radeon_uvd_free_handles(struct radeon_device *rdev,
1567 struct drm_file *filp);
1568int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1569void radeon_uvd_note_usage(struct radeon_device *rdev);
1570int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1571 unsigned vclk, unsigned dclk,
1572 unsigned vco_min, unsigned vco_max,
1573 unsigned fb_factor, unsigned fb_mask,
1574 unsigned pd_min, unsigned pd_max,
1575 unsigned pd_even,
1576 unsigned *optimal_fb_div,
1577 unsigned *optimal_vclk_div,
1578 unsigned *optimal_dclk_div);
1579int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1580 unsigned cg_upll_func_cntl);
1581
1671void radeon_uvd_free_handles(struct radeon_device *rdev,
1672 struct drm_file *filp);
1673int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1674void radeon_uvd_note_usage(struct radeon_device *rdev);
1675int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1676 unsigned vclk, unsigned dclk,
1677 unsigned vco_min, unsigned vco_max,
1678 unsigned fb_factor, unsigned fb_mask,
1679 unsigned pd_min, unsigned pd_max,
1680 unsigned pd_even,
1681 unsigned *optimal_fb_div,
1682 unsigned *optimal_vclk_div,
1683 unsigned *optimal_dclk_div);
1684int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1685 unsigned cg_upll_func_cntl);
1686
1687/*
1688 * VCE
1689 */
1690#define RADEON_MAX_VCE_HANDLES 16
1691#define RADEON_VCE_STACK_SIZE (1024*1024)
1692#define RADEON_VCE_HEAP_SIZE (4*1024*1024)
1693
1694struct radeon_vce {
1695 struct radeon_bo *vcpu_bo;
1696 uint64_t gpu_addr;
1697 unsigned fw_version;
1698 unsigned fb_version;
1699 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1700 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
1701 unsigned img_size[RADEON_MAX_VCE_HANDLES];
1702 struct delayed_work idle_work;
1703};
1704
1705int radeon_vce_init(struct radeon_device *rdev);
1706void radeon_vce_fini(struct radeon_device *rdev);
1707int radeon_vce_suspend(struct radeon_device *rdev);
1708int radeon_vce_resume(struct radeon_device *rdev);
1709int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1710 uint32_t handle, struct radeon_fence **fence);
1711int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1712 uint32_t handle, struct radeon_fence **fence);
1713void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1714void radeon_vce_note_usage(struct radeon_device *rdev);
1715int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1716int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1717bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1718 struct radeon_ring *ring,
1719 struct radeon_semaphore *semaphore,
1720 bool emit_wait);
1721void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1722void radeon_vce_fence_emit(struct radeon_device *rdev,
1723 struct radeon_fence *fence);
1724int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1725int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1726
1582struct r600_audio_pin {
1583 int channels;
1584 int rate;
1585 int bits_per_sample;
1586 u8 status_bits;
1587 u8 category_code;
1588 u32 offset;
1589 bool connected;

--- 16 unchanged lines hidden (view full) ---

1606 * Testing
1607 */
1608void radeon_test_moves(struct radeon_device *rdev);
1609void radeon_test_ring_sync(struct radeon_device *rdev,
1610 struct radeon_ring *cpA,
1611 struct radeon_ring *cpB);
1612void radeon_test_syncing(struct radeon_device *rdev);
1613
1727struct r600_audio_pin {
1728 int channels;
1729 int rate;
1730 int bits_per_sample;
1731 u8 status_bits;
1732 u8 category_code;
1733 u32 offset;
1734 bool connected;

--- 16 unchanged lines hidden (view full) ---

1751 * Testing
1752 */
1753void radeon_test_moves(struct radeon_device *rdev);
1754void radeon_test_ring_sync(struct radeon_device *rdev,
1755 struct radeon_ring *cpA,
1756 struct radeon_ring *cpB);
1757void radeon_test_syncing(struct radeon_device *rdev);
1758
1759/*
1760 * MMU Notifier
1761 */
1762int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1763void radeon_mn_unregister(struct radeon_bo *bo);
1614
1615/*
1616 * Debugfs
1617 */
1618struct radeon_debugfs {
1619 struct drm_info_list *files;
1620 unsigned num_files;
1621};

--- 14 unchanged lines hidden (view full) ---

1636
1637 /* validating and patching of IBs */
1638 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1639 int (*cs_parse)(struct radeon_cs_parser *p);
1640
1641 /* command emmit functions */
1642 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1643 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1764
1765/*
1766 * Debugfs
1767 */
1768struct radeon_debugfs {
1769 struct drm_info_list *files;
1770 unsigned num_files;
1771};

--- 14 unchanged lines hidden (view full) ---

1786
1787 /* validating and patching of IBs */
1788 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1789 int (*cs_parse)(struct radeon_cs_parser *p);
1790
1791 /* command emmit functions */
1792 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1793 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1794 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1644 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1645 struct radeon_semaphore *semaphore, bool emit_wait);
1646 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1647
1648 /* testing functions */
1649 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1650 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1651 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);

--- 7 unchanged lines hidden (view full) ---

1659 */
1660struct radeon_asic {
1661 int (*init)(struct radeon_device *rdev);
1662 void (*fini)(struct radeon_device *rdev);
1663 int (*resume)(struct radeon_device *rdev);
1664 int (*suspend)(struct radeon_device *rdev);
1665 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1666 int (*asic_reset)(struct radeon_device *rdev);
1795 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1796 struct radeon_semaphore *semaphore, bool emit_wait);
1797 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1798
1799 /* testing functions */
1800 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1801 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1802 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);

--- 7 unchanged lines hidden (view full) ---

1810 */
1811struct radeon_asic {
1812 int (*init)(struct radeon_device *rdev);
1813 void (*fini)(struct radeon_device *rdev);
1814 int (*resume)(struct radeon_device *rdev);
1815 int (*suspend)(struct radeon_device *rdev);
1816 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1817 int (*asic_reset)(struct radeon_device *rdev);
1667 /* ioctl hw specific callback. Some hw might want to perform special
1668 * operation on specific ioctl. For instance on wait idle some hw
1669 * might want to perform and HDP flush through MMIO as it seems that
1670 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1671 * through ring.
1672 */
1673 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1818 /* Flush the HDP cache via MMIO */
1819 void (*mmio_hdp_flush)(struct radeon_device *rdev);
1674 /* check if 3D engine is idle */
1675 bool (*gui_idle)(struct radeon_device *rdev);
1676 /* wait for mc_idle */
1677 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1678 /* get the reference clock */
1679 u32 (*get_xclk)(struct radeon_device *rdev);
1680 /* get the gpu clock counter */
1681 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1682 /* gart */
1683 struct {
1684 void (*tlb_flush)(struct radeon_device *rdev);
1820 /* check if 3D engine is idle */
1821 bool (*gui_idle)(struct radeon_device *rdev);
1822 /* wait for mc_idle */
1823 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1824 /* get the reference clock */
1825 u32 (*get_xclk)(struct radeon_device *rdev);
1826 /* get the gpu clock counter */
1827 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1828 /* gart */
1829 struct {
1830 void (*tlb_flush)(struct radeon_device *rdev);
1685 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1831 void (*set_page)(struct radeon_device *rdev, unsigned i,
1832 uint64_t addr, uint32_t flags);
1686 } gart;
1687 struct {
1688 int (*init)(struct radeon_device *rdev);
1689 void (*fini)(struct radeon_device *rdev);
1833 } gart;
1834 struct {
1835 int (*init)(struct radeon_device *rdev);
1836 void (*fini)(struct radeon_device *rdev);
1690 void (*set_page)(struct radeon_device *rdev,
1691 struct radeon_ib *ib,
1692 uint64_t pe,
1693 uint64_t addr, unsigned count,
1694 uint32_t incr, uint32_t flags);
1837 void (*copy_pages)(struct radeon_device *rdev,
1838 struct radeon_ib *ib,
1839 uint64_t pe, uint64_t src,
1840 unsigned count);
1841 void (*write_pages)(struct radeon_device *rdev,
1842 struct radeon_ib *ib,
1843 uint64_t pe,
1844 uint64_t addr, unsigned count,
1845 uint32_t incr, uint32_t flags);
1846 void (*set_pages)(struct radeon_device *rdev,
1847 struct radeon_ib *ib,
1848 uint64_t pe,
1849 uint64_t addr, unsigned count,
1850 uint32_t incr, uint32_t flags);
1851 void (*pad_ib)(struct radeon_ib *ib);
1695 } vm;
1696 /* ring specific callbacks */
1697 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1698 /* irqs */
1699 struct {
1700 int (*set)(struct radeon_device *rdev);
1701 int (*process)(struct radeon_device *rdev);
1702 } irq;

--- 10 unchanged lines hidden (view full) ---

1713 /* get backlight level */
1714 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1715 /* audio callbacks */
1716 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1717 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1718 } display;
1719 /* copy functions for bo handling */
1720 struct {
1852 } vm;
1853 /* ring specific callbacks */
1854 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1855 /* irqs */
1856 struct {
1857 int (*set)(struct radeon_device *rdev);
1858 int (*process)(struct radeon_device *rdev);
1859 } irq;

--- 10 unchanged lines hidden (view full) ---

1870 /* get backlight level */
1871 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1872 /* audio callbacks */
1873 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1874 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1875 } display;
1876 /* copy functions for bo handling */
1877 struct {
1721 int (*blit)(struct radeon_device *rdev,
1722 uint64_t src_offset,
1723 uint64_t dst_offset,
1724 unsigned num_gpu_pages,
1725 struct radeon_fence **fence);
1878 struct radeon_fence *(*blit)(struct radeon_device *rdev,
1879 uint64_t src_offset,
1880 uint64_t dst_offset,
1881 unsigned num_gpu_pages,
1882 struct reservation_object *resv);
1726 u32 blit_ring_index;
1883 u32 blit_ring_index;
1727 int (*dma)(struct radeon_device *rdev,
1728 uint64_t src_offset,
1729 uint64_t dst_offset,
1730 unsigned num_gpu_pages,
1731 struct radeon_fence **fence);
1884 struct radeon_fence *(*dma)(struct radeon_device *rdev,
1885 uint64_t src_offset,
1886 uint64_t dst_offset,
1887 unsigned num_gpu_pages,
1888 struct reservation_object *resv);
1732 u32 dma_ring_index;
1733 /* method used for bo copy */
1889 u32 dma_ring_index;
1890 /* method used for bo copy */
1734 int (*copy)(struct radeon_device *rdev,
1735 uint64_t src_offset,
1736 uint64_t dst_offset,
1737 unsigned num_gpu_pages,
1738 struct radeon_fence **fence);
1891 struct radeon_fence *(*copy)(struct radeon_device *rdev,
1892 uint64_t src_offset,
1893 uint64_t dst_offset,
1894 unsigned num_gpu_pages,
1895 struct reservation_object *resv);
1739 /* ring used for bo copies */
1740 u32 copy_ring_index;
1741 } copy;
1742 /* surfaces */
1743 struct {
1744 int (*set_reg)(struct radeon_device *rdev, int reg,
1745 uint32_t tiling_flags, uint32_t pitch,
1746 uint32_t offset, uint32_t obj_size);

--- 16 unchanged lines hidden (view full) ---

1763 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1764 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1765 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1766 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1767 int (*get_pcie_lanes)(struct radeon_device *rdev);
1768 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1769 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1770 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1896 /* ring used for bo copies */
1897 u32 copy_ring_index;
1898 } copy;
1899 /* surfaces */
1900 struct {
1901 int (*set_reg)(struct radeon_device *rdev, int reg,
1902 uint32_t tiling_flags, uint32_t pitch,
1903 uint32_t offset, uint32_t obj_size);

--- 16 unchanged lines hidden (view full) ---

1920 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1921 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1922 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1923 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1924 int (*get_pcie_lanes)(struct radeon_device *rdev);
1925 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1926 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1927 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1928 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1771 int (*get_temperature)(struct radeon_device *rdev);
1772 } pm;
1773 /* dynamic power management */
1774 struct {
1775 int (*init)(struct radeon_device *rdev);
1776 void (*setup_asic)(struct radeon_device *rdev);
1777 int (*enable)(struct radeon_device *rdev);
1929 int (*get_temperature)(struct radeon_device *rdev);
1930 } pm;
1931 /* dynamic power management */
1932 struct {
1933 int (*init)(struct radeon_device *rdev);
1934 void (*setup_asic)(struct radeon_device *rdev);
1935 int (*enable)(struct radeon_device *rdev);
1936 int (*late_enable)(struct radeon_device *rdev);
1778 void (*disable)(struct radeon_device *rdev);
1779 int (*pre_set_power_state)(struct radeon_device *rdev);
1780 int (*set_power_state)(struct radeon_device *rdev);
1781 void (*post_set_power_state)(struct radeon_device *rdev);
1782 void (*display_configuration_changed)(struct radeon_device *rdev);
1783 void (*fini)(struct radeon_device *rdev);
1784 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1785 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1786 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1787 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1788 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1789 bool (*vblank_too_short)(struct radeon_device *rdev);
1790 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1791 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1792 } dpm;
1793 /* pageflipping */
1794 struct {
1937 void (*disable)(struct radeon_device *rdev);
1938 int (*pre_set_power_state)(struct radeon_device *rdev);
1939 int (*set_power_state)(struct radeon_device *rdev);
1940 void (*post_set_power_state)(struct radeon_device *rdev);
1941 void (*display_configuration_changed)(struct radeon_device *rdev);
1942 void (*fini)(struct radeon_device *rdev);
1943 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1944 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1945 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1946 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1947 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1948 bool (*vblank_too_short)(struct radeon_device *rdev);
1949 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1950 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1951 } dpm;
1952 /* pageflipping */
1953 struct {
1795 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1796 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1797 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1954 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1955 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
1798 } pflip;
1799};
1800
1801/*
1802 * Asic structures
1803 */
1804struct r100_asic {
1805 const unsigned *reg_safe_bm;

--- 22 unchanged lines hidden (view full) ---

1828 unsigned sx_max_export_pos_size;
1829 unsigned sx_max_export_smx_size;
1830 unsigned sq_num_cf_insts;
1831 unsigned tiling_nbanks;
1832 unsigned tiling_npipes;
1833 unsigned tiling_group_size;
1834 unsigned tile_config;
1835 unsigned backend_map;
1956 } pflip;
1957};
1958
1959/*
1960 * Asic structures
1961 */
1962struct r100_asic {
1963 const unsigned *reg_safe_bm;

--- 22 unchanged lines hidden (view full) ---

1986 unsigned sx_max_export_pos_size;
1987 unsigned sx_max_export_smx_size;
1988 unsigned sq_num_cf_insts;
1989 unsigned tiling_nbanks;
1990 unsigned tiling_npipes;
1991 unsigned tiling_group_size;
1992 unsigned tile_config;
1993 unsigned backend_map;
1994 unsigned active_simds;
1836};
1837
1838struct rv770_asic {
1839 unsigned max_pipes;
1840 unsigned max_tile_pipes;
1841 unsigned max_simds;
1842 unsigned max_backends;
1843 unsigned max_gprs;

--- 9 unchanged lines hidden (view full) ---

1853 unsigned sc_prim_fifo_size;
1854 unsigned sc_hiz_tile_fifo_size;
1855 unsigned sc_earlyz_tile_fifo_fize;
1856 unsigned tiling_nbanks;
1857 unsigned tiling_npipes;
1858 unsigned tiling_group_size;
1859 unsigned tile_config;
1860 unsigned backend_map;
1995};
1996
1997struct rv770_asic {
1998 unsigned max_pipes;
1999 unsigned max_tile_pipes;
2000 unsigned max_simds;
2001 unsigned max_backends;
2002 unsigned max_gprs;

--- 9 unchanged lines hidden (view full) ---

2012 unsigned sc_prim_fifo_size;
2013 unsigned sc_hiz_tile_fifo_size;
2014 unsigned sc_earlyz_tile_fifo_fize;
2015 unsigned tiling_nbanks;
2016 unsigned tiling_npipes;
2017 unsigned tiling_group_size;
2018 unsigned tile_config;
2019 unsigned backend_map;
2020 unsigned active_simds;
1861};
1862
1863struct evergreen_asic {
1864 unsigned num_ses;
1865 unsigned max_pipes;
1866 unsigned max_tile_pipes;
1867 unsigned max_simds;
1868 unsigned max_backends;

--- 10 unchanged lines hidden (view full) ---

1879 unsigned sc_prim_fifo_size;
1880 unsigned sc_hiz_tile_fifo_size;
1881 unsigned sc_earlyz_tile_fifo_size;
1882 unsigned tiling_nbanks;
1883 unsigned tiling_npipes;
1884 unsigned tiling_group_size;
1885 unsigned tile_config;
1886 unsigned backend_map;
2021};
2022
2023struct evergreen_asic {
2024 unsigned num_ses;
2025 unsigned max_pipes;
2026 unsigned max_tile_pipes;
2027 unsigned max_simds;
2028 unsigned max_backends;

--- 10 unchanged lines hidden (view full) ---

2039 unsigned sc_prim_fifo_size;
2040 unsigned sc_hiz_tile_fifo_size;
2041 unsigned sc_earlyz_tile_fifo_size;
2042 unsigned tiling_nbanks;
2043 unsigned tiling_npipes;
2044 unsigned tiling_group_size;
2045 unsigned tile_config;
2046 unsigned backend_map;
2047 unsigned active_simds;
1887};
1888
1889struct cayman_asic {
1890 unsigned max_shader_engines;
1891 unsigned max_pipes_per_simd;
1892 unsigned max_tile_pipes;
1893 unsigned max_simds_per_se;
1894 unsigned max_backends_per_se;

--- 22 unchanged lines hidden (view full) ---

1917 unsigned num_texture_channel_caches;
1918 unsigned mem_max_burst_length_bytes;
1919 unsigned mem_row_size_in_kb;
1920 unsigned shader_engine_tile_size;
1921 unsigned num_gpus;
1922 unsigned multi_gpu_tile_size;
1923
1924 unsigned tile_config;
2048};
2049
2050struct cayman_asic {
2051 unsigned max_shader_engines;
2052 unsigned max_pipes_per_simd;
2053 unsigned max_tile_pipes;
2054 unsigned max_simds_per_se;
2055 unsigned max_backends_per_se;

--- 22 unchanged lines hidden (view full) ---

2078 unsigned num_texture_channel_caches;
2079 unsigned mem_max_burst_length_bytes;
2080 unsigned mem_row_size_in_kb;
2081 unsigned shader_engine_tile_size;
2082 unsigned num_gpus;
2083 unsigned multi_gpu_tile_size;
2084
2085 unsigned tile_config;
2086 unsigned active_simds;
1925};
1926
1927struct si_asic {
1928 unsigned max_shader_engines;
1929 unsigned max_tile_pipes;
1930 unsigned max_cu_per_sh;
1931 unsigned max_sh_per_se;
1932 unsigned max_backends_per_se;

--- 14 unchanged lines hidden (view full) ---

1947 unsigned mem_max_burst_length_bytes;
1948 unsigned mem_row_size_in_kb;
1949 unsigned shader_engine_tile_size;
1950 unsigned num_gpus;
1951 unsigned multi_gpu_tile_size;
1952
1953 unsigned tile_config;
1954 uint32_t tile_mode_array[32];
2087};
2088
2089struct si_asic {
2090 unsigned max_shader_engines;
2091 unsigned max_tile_pipes;
2092 unsigned max_cu_per_sh;
2093 unsigned max_sh_per_se;
2094 unsigned max_backends_per_se;

--- 14 unchanged lines hidden (view full) ---

2109 unsigned mem_max_burst_length_bytes;
2110 unsigned mem_row_size_in_kb;
2111 unsigned shader_engine_tile_size;
2112 unsigned num_gpus;
2113 unsigned multi_gpu_tile_size;
2114
2115 unsigned tile_config;
2116 uint32_t tile_mode_array[32];
2117 uint32_t active_cus;
1955};
1956
1957struct cik_asic {
1958 unsigned max_shader_engines;
1959 unsigned max_tile_pipes;
1960 unsigned max_cu_per_sh;
1961 unsigned max_sh_per_se;
1962 unsigned max_backends_per_se;

--- 15 unchanged lines hidden (view full) ---

1978 unsigned mem_row_size_in_kb;
1979 unsigned shader_engine_tile_size;
1980 unsigned num_gpus;
1981 unsigned multi_gpu_tile_size;
1982
1983 unsigned tile_config;
1984 uint32_t tile_mode_array[32];
1985 uint32_t macrotile_mode_array[16];
2118};
2119
2120struct cik_asic {
2121 unsigned max_shader_engines;
2122 unsigned max_tile_pipes;
2123 unsigned max_cu_per_sh;
2124 unsigned max_sh_per_se;
2125 unsigned max_backends_per_se;

--- 15 unchanged lines hidden (view full) ---

2141 unsigned mem_row_size_in_kb;
2142 unsigned shader_engine_tile_size;
2143 unsigned num_gpus;
2144 unsigned multi_gpu_tile_size;
2145
2146 unsigned tile_config;
2147 uint32_t tile_mode_array[32];
2148 uint32_t macrotile_mode_array[16];
2149 uint32_t active_cus;
1986};
1987
1988union radeon_asic_config {
1989 struct r300_asic r300;
1990 struct r100_asic r100;
1991 struct r600_asic r600;
1992 struct rv770_asic rv770;
1993 struct evergreen_asic evergreen;

--- 11 unchanged lines hidden (view full) ---

2005
2006/*
2007 * IOCTL.
2008 */
2009int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2010 struct drm_file *filp);
2011int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2012 struct drm_file *filp);
2150};
2151
2152union radeon_asic_config {
2153 struct r300_asic r300;
2154 struct r100_asic r100;
2155 struct r600_asic r600;
2156 struct rv770_asic rv770;
2157 struct evergreen_asic evergreen;

--- 11 unchanged lines hidden (view full) ---

2169
2170/*
2171 * IOCTL.
2172 */
2173int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2174 struct drm_file *filp);
2175int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2176 struct drm_file *filp);
2177int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2178 struct drm_file *filp);
2013int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2014 struct drm_file *file_priv);
2015int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2016 struct drm_file *file_priv);
2017int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2018 struct drm_file *file_priv);
2019int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2020 struct drm_file *file_priv);
2021int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2022 struct drm_file *filp);
2023int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2024 struct drm_file *filp);
2025int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2026 struct drm_file *filp);
2027int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2028 struct drm_file *filp);
2029int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2030 struct drm_file *filp);
2179int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2180 struct drm_file *file_priv);
2181int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2182 struct drm_file *file_priv);
2183int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2184 struct drm_file *file_priv);
2185int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2186 struct drm_file *file_priv);
2187int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2188 struct drm_file *filp);
2189int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2190 struct drm_file *filp);
2191int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2192 struct drm_file *filp);
2193int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2194 struct drm_file *filp);
2195int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2196 struct drm_file *filp);
2197int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2198 struct drm_file *filp);
2031int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2032int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2033 struct drm_file *filp);
2034int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2035 struct drm_file *filp);
2036
2037/* VRAM scratch page for HDP bug, default vram page */
2038struct r600_vram_scratch {

--- 120 unchanged lines hidden (view full) ---

2159 struct radeon_mc mc;
2160 struct radeon_gart gart;
2161 struct radeon_mode_info mode_info;
2162 struct radeon_scratch scratch;
2163 struct radeon_doorbell doorbell;
2164 struct radeon_mman mman;
2165 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2166 wait_queue_head_t fence_queue;
2199int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2200int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2201 struct drm_file *filp);
2202int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2203 struct drm_file *filp);
2204
2205/* VRAM scratch page for HDP bug, default vram page */
2206struct r600_vram_scratch {

--- 120 unchanged lines hidden (view full) ---

2327 struct radeon_mc mc;
2328 struct radeon_gart gart;
2329 struct radeon_mode_info mode_info;
2330 struct radeon_scratch scratch;
2331 struct radeon_doorbell doorbell;
2332 struct radeon_mman mman;
2333 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2334 wait_queue_head_t fence_queue;
2335 unsigned fence_context;
2167 struct mutex ring_lock;
2168 struct radeon_ring ring[RADEON_NUM_RINGS];
2169 bool ib_pool_ready;
2170 struct radeon_sa_manager ring_tmp_bo;
2171 struct radeon_irq irq;
2172 struct radeon_asic *asic;
2173 struct radeon_gem gem;
2174 struct radeon_pm pm;
2175 struct radeon_uvd uvd;
2336 struct mutex ring_lock;
2337 struct radeon_ring ring[RADEON_NUM_RINGS];
2338 bool ib_pool_ready;
2339 struct radeon_sa_manager ring_tmp_bo;
2340 struct radeon_irq irq;
2341 struct radeon_asic *asic;
2342 struct radeon_gem gem;
2343 struct radeon_pm pm;
2344 struct radeon_uvd uvd;
2345 struct radeon_vce vce;
2176 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2177 struct radeon_wb wb;
2178 struct radeon_dummy_page dummy_page;
2179 bool shutdown;
2180 bool suspend;
2181 bool need_dma32;
2182 bool accel_working;
2183 bool fastfb_working; /* IGP feature*/
2346 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2347 struct radeon_wb wb;
2348 struct radeon_dummy_page dummy_page;
2349 bool shutdown;
2350 bool suspend;
2351 bool need_dma32;
2352 bool accel_working;
2353 bool fastfb_working; /* IGP feature*/
2184 bool needs_reset;
2354 bool needs_reset, in_reset;
2185 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2186 const struct firmware *me_fw; /* all family ME firmware */
2187 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2188 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2189 const struct firmware *mc_fw; /* NI MC firmware */
2190 const struct firmware *ce_fw; /* SI CE firmware */
2191 const struct firmware *mec_fw; /* CIK MEC firmware */
2355 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2356 const struct firmware *me_fw; /* all family ME firmware */
2357 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2358 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2359 const struct firmware *mc_fw; /* NI MC firmware */
2360 const struct firmware *ce_fw; /* SI CE firmware */
2361 const struct firmware *mec_fw; /* CIK MEC firmware */
2362 const struct firmware *mec2_fw; /* KV MEC2 firmware */
2192 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2193 const struct firmware *smc_fw; /* SMC firmware */
2194 const struct firmware *uvd_fw; /* UVD firmware */
2363 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2364 const struct firmware *smc_fw; /* SMC firmware */
2365 const struct firmware *uvd_fw; /* UVD firmware */
2366 const struct firmware *vce_fw; /* VCE firmware */
2367 bool new_fw;
2195 struct r600_vram_scratch vram_scratch;
2196 int msi_enabled; /* msi enabled */
2197 struct r600_ih ih; /* r6/700 interrupt ring */
2198 struct radeon_rlc rlc;
2199 struct radeon_mec mec;
2200 struct work_struct hotplug_work;
2201 struct work_struct audio_work;
2368 struct r600_vram_scratch vram_scratch;
2369 int msi_enabled; /* msi enabled */
2370 struct r600_ih ih; /* r6/700 interrupt ring */
2371 struct radeon_rlc rlc;
2372 struct radeon_mec mec;
2373 struct work_struct hotplug_work;
2374 struct work_struct audio_work;
2202 struct work_struct reset_work;
2203 int num_crtc; /* number of crtcs */
2204 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2205 bool has_uvd;
2206 struct r600_audio audio; /* audio stuff */
2207 struct notifier_block acpi_nb;
2208 /* only one userspace can use Hyperz features or CMASK at a time */
2209 struct drm_file *hyperz_filp;
2210 struct drm_file *cmask_filp;
2211 /* i2c buses */
2212 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2213 /* debugfs */
2214 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2215 unsigned debugfs_count;
2216 /* virtual memory */
2217 struct radeon_vm_manager vm_manager;
2218 struct mutex gpu_clock_mutex;
2375 int num_crtc; /* number of crtcs */
2376 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2377 bool has_uvd;
2378 struct r600_audio audio; /* audio stuff */
2379 struct notifier_block acpi_nb;
2380 /* only one userspace can use Hyperz features or CMASK at a time */
2381 struct drm_file *hyperz_filp;
2382 struct drm_file *cmask_filp;
2383 /* i2c buses */
2384 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2385 /* debugfs */
2386 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2387 unsigned debugfs_count;
2388 /* virtual memory */
2389 struct radeon_vm_manager vm_manager;
2390 struct mutex gpu_clock_mutex;
2391 /* memory stats */
2392 atomic64_t vram_usage;
2393 atomic64_t gtt_usage;
2394 atomic64_t num_bytes_moved;
2219 /* ACPI interface */
2220 struct radeon_atif atif;
2221 struct radeon_atcs atcs;
2222 /* srbm instance registers */
2223 struct mutex srbm_mutex;
2224 /* clock, powergating flags */
2225 u32 cg_flags;
2226 u32 pg_flags;
2227
2228 struct dev_pm_domain vga_pm_domain;
2229 bool have_disp_power_ref;
2395 /* ACPI interface */
2396 struct radeon_atif atif;
2397 struct radeon_atcs atcs;
2398 /* srbm instance registers */
2399 struct mutex srbm_mutex;
2400 /* clock, powergating flags */
2401 u32 cg_flags;
2402 u32 pg_flags;
2403
2404 struct dev_pm_domain vga_pm_domain;
2405 bool have_disp_power_ref;
2406 u32 px_quirk_flags;
2407
2408 /* tracking pinned memory */
2409 u64 vram_pin_size;
2410 u64 gart_pin_size;
2411
2412 struct mutex mn_lock;
2413 DECLARE_HASHTABLE(mn_hash, 7);
2230};
2231
2414};
2415
2416bool radeon_is_px(struct drm_device *dev);
2232int radeon_device_init(struct radeon_device *rdev,
2233 struct drm_device *ddev,
2234 struct pci_dev *pdev,
2235 uint32_t flags);
2236void radeon_device_fini(struct radeon_device *rdev);
2237int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2238
2417int radeon_device_init(struct radeon_device *rdev,
2418 struct drm_device *ddev,
2419 struct pci_dev *pdev,
2420 uint32_t flags);
2421void radeon_device_fini(struct radeon_device *rdev);
2422int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2423
2239uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2240 bool always_indirect);
2241void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2242 bool always_indirect);
2424#define RADEON_MIN_MMIO_SIZE 0x10000
2425
2426static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2427 bool always_indirect)
2428{
2429 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2430 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2431 return readl(((void __iomem *)rdev->rmmio) + reg);
2432 else {
2433 unsigned long flags;
2434 uint32_t ret;
2435
2436 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2437 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2438 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2439 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2440
2441 return ret;
2442 }
2443}
2444
2445static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2446 bool always_indirect)
2447{
2448 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2449 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2450 else {
2451 unsigned long flags;
2452
2453 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2454 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2455 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2456 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2457 }
2458}
2459
2243u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2244void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2245
2246u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2247void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2248
2249/*
2250 * Cast helper
2251 */
2460u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2461void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2462
2463u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2464void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2465
2466/*
2467 * Cast helper
2468 */
2252#define to_radeon_fence(p) ((struct radeon_fence *)(p))
2469extern const struct fence_ops radeon_fence_ops;
2253
2470
2471static inline struct radeon_fence *to_radeon_fence(struct fence *f)
2472{
2473 struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2474
2475 if (__f->base.ops == &radeon_fence_ops)
2476 return __f;
2477
2478 return NULL;
2479}
2480
2254/*
2255 * Registers read & write functions.
2256 */
2257#define RREG8(reg) readb((rdev->rmmio) + (reg))
2258#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2259#define RREG16(reg) readw((rdev->rmmio) + (reg))
2260#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2261#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)

--- 272 unchanged lines hidden (view full) ---

2534 (rdev->flags & RADEON_IS_IGP))
2535#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2536#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2537#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2538 (rdev->flags & RADEON_IS_IGP))
2539#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2540#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2541#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2481/*
2482 * Registers read & write functions.
2483 */
2484#define RREG8(reg) readb((rdev->rmmio) + (reg))
2485#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2486#define RREG16(reg) readw((rdev->rmmio) + (reg))
2487#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2488#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)

--- 272 unchanged lines hidden (view full) ---

2761 (rdev->flags & RADEON_IS_IGP))
2762#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2763#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2764#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2765 (rdev->flags & RADEON_IS_IGP))
2766#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2767#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2768#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2769#define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2770#define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2771#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2772 (rdev->family == CHIP_MULLINS))
2542
2543#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2544 (rdev->ddev->pdev->device == 0x6850) || \
2545 (rdev->ddev->pdev->device == 0x6858) || \
2546 (rdev->ddev->pdev->device == 0x6859) || \
2547 (rdev->ddev->pdev->device == 0x6840) || \
2548 (rdev->ddev->pdev->device == 0x6841) || \
2549 (rdev->ddev->pdev->device == 0x6842) || \

--- 10 unchanged lines hidden (view full) ---

2560void radeon_combios_fini(struct radeon_device *rdev);
2561int radeon_atombios_init(struct radeon_device *rdev);
2562void radeon_atombios_fini(struct radeon_device *rdev);
2563
2564
2565/*
2566 * RING helpers.
2567 */
2773
2774#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2775 (rdev->ddev->pdev->device == 0x6850) || \
2776 (rdev->ddev->pdev->device == 0x6858) || \
2777 (rdev->ddev->pdev->device == 0x6859) || \
2778 (rdev->ddev->pdev->device == 0x6840) || \
2779 (rdev->ddev->pdev->device == 0x6841) || \
2780 (rdev->ddev->pdev->device == 0x6842) || \

--- 10 unchanged lines hidden (view full) ---

2791void radeon_combios_fini(struct radeon_device *rdev);
2792int radeon_atombios_init(struct radeon_device *rdev);
2793void radeon_atombios_fini(struct radeon_device *rdev);
2794
2795
2796/*
2797 * RING helpers.
2798 */
2568#if DRM_DEBUG_CODE == 0
2799
2800/**
2801 * radeon_ring_write - write a value to the ring
2802 *
2803 * @ring: radeon_ring structure holding ring information
2804 * @v: dword (dw) value to write
2805 *
2806 * Write a value to the requested ring buffer (all asics).
2807 */
2569static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2570{
2808static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2809{
2810 if (ring->count_dw <= 0)
2811 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2812
2571 ring->ring[ring->wptr++] = v;
2572 ring->wptr &= ring->ptr_mask;
2573 ring->count_dw--;
2574 ring->ring_free_dw--;
2575}
2813 ring->ring[ring->wptr++] = v;
2814 ring->wptr &= ring->ptr_mask;
2815 ring->count_dw--;
2816 ring->ring_free_dw--;
2817}
2576#else
2577/* With debugging this is just too big to inline */
2578void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
2579#endif
2580
2581/*
2582 * ASICs macro.
2583 */
2584#define radeon_init(rdev) (rdev)->asic->init((rdev))
2585#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2586#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2587#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2588#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2589#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2590#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2591#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2818
2819/*
2820 * ASICs macro.
2821 */
2822#define radeon_init(rdev) (rdev)->asic->init((rdev))
2823#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2824#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2825#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2826#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2827#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2828#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2829#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2592#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
2830#define radeon_gart_set_page(rdev, i, p, f) (rdev)->asic->gart.set_page((rdev), (i), (p), (f))
2593#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2594#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2831#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2832#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2595#define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2833#define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2834#define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2835#define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2836#define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
2596#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2597#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2598#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2599#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2600#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2601#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2602#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2603#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2604#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2605#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2606#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2607#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2608#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2609#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2610#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2611#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2612#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2613#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2614#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2837#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2838#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2839#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2840#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2841#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2842#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2843#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2844#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2845#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2846#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2847#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2848#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2849#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2850#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2851#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2852#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2853#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2854#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2855#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2615#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2616#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2617#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2856#define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
2857#define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2858#define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
2618#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2619#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2620#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2621#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2622#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2623#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2624#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2625#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2626#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2627#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2628#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2859#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2860#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2861#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2862#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2863#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2864#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2865#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2866#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2867#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2868#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2869#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2870#define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2629#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2630#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2631#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2632#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2633#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2634#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2635#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2636#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2637#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2638#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2639#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2640#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2641#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2642#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2871#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2872#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2873#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2874#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2875#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2876#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2877#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2878#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2879#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2880#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2881#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2882#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2883#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2884#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2643#define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
2644#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2885#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2645#define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
2886#define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2646#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2647#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2648#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2649#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2650#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2651#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2652#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2887#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2888#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2889#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2890#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2891#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2892#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2893#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2894#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2653#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2654#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2655#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2656#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2657#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2658#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2659#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2660#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2661#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2662#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2663#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2664#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2665#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2666#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2667
2668/* Common functions */
2669/* AGP */
2670extern int radeon_gpu_reset(struct radeon_device *rdev);
2895#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2896#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2897#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2898#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2899#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2900#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2901#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2902#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2903#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2904#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2905#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2906#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2907#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2908#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2909
2910/* Common functions */
2911/* AGP */
2912extern int radeon_gpu_reset(struct radeon_device *rdev);
2913extern void radeon_pci_config_reset(struct radeon_device *rdev);
2671extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2672extern void radeon_agp_disable(struct radeon_device *rdev);
2673extern int radeon_modeset_init(struct radeon_device *rdev);
2674extern void radeon_modeset_fini(struct radeon_device *rdev);
2675extern bool radeon_card_posted(struct radeon_device *rdev);
2676extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2677extern void radeon_update_display_priority(struct radeon_device *rdev);
2678extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2679extern void radeon_scratch_init(struct radeon_device *rdev);
2680extern void radeon_wb_fini(struct radeon_device *rdev);
2681extern int radeon_wb_init(struct radeon_device *rdev);
2682extern void radeon_wb_disable(struct radeon_device *rdev);
2683extern void radeon_surface_init(struct radeon_device *rdev);
2684extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2685extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2686extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2687extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2688extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2914extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2915extern void radeon_agp_disable(struct radeon_device *rdev);
2916extern int radeon_modeset_init(struct radeon_device *rdev);
2917extern void radeon_modeset_fini(struct radeon_device *rdev);
2918extern bool radeon_card_posted(struct radeon_device *rdev);
2919extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2920extern void radeon_update_display_priority(struct radeon_device *rdev);
2921extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2922extern void radeon_scratch_init(struct radeon_device *rdev);
2923extern void radeon_wb_fini(struct radeon_device *rdev);
2924extern int radeon_wb_init(struct radeon_device *rdev);
2925extern void radeon_wb_disable(struct radeon_device *rdev);
2926extern void radeon_surface_init(struct radeon_device *rdev);
2927extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2928extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2929extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2930extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2931extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2932extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2933 uint32_t flags);
2934extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
2935extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
2689extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2690extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2691extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2692extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2693extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2694extern void radeon_program_register_sequence(struct radeon_device *rdev,
2695 const u32 *registers,
2696 const u32 array_size);
2697
2698/*
2699 * vm
2700 */
2701int radeon_vm_manager_init(struct radeon_device *rdev);
2702void radeon_vm_manager_fini(struct radeon_device *rdev);
2936extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2937extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2938extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2939extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2940extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2941extern void radeon_program_register_sequence(struct radeon_device *rdev,
2942 const u32 *registers,
2943 const u32 array_size);
2944
2945/*
2946 * vm
2947 */
2948int radeon_vm_manager_init(struct radeon_device *rdev);
2949void radeon_vm_manager_fini(struct radeon_device *rdev);
2703void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2950int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2704void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2951void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2705int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
2706void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
2952struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
2953 struct radeon_vm *vm,
2954 struct list_head *head);
2707struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2708 struct radeon_vm *vm, int ring);
2955struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2956 struct radeon_vm *vm, int ring);
2957void radeon_vm_flush(struct radeon_device *rdev,
2958 struct radeon_vm *vm,
2959 int ring);
2709void radeon_vm_fence(struct radeon_device *rdev,
2710 struct radeon_vm *vm,
2711 struct radeon_fence *fence);
2712uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2960void radeon_vm_fence(struct radeon_device *rdev,
2961 struct radeon_vm *vm,
2962 struct radeon_fence *fence);
2963uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2964int radeon_vm_update_page_directory(struct radeon_device *rdev,
2965 struct radeon_vm *vm);
2966int radeon_vm_clear_freed(struct radeon_device *rdev,
2967 struct radeon_vm *vm);
2968int radeon_vm_clear_invalids(struct radeon_device *rdev,
2969 struct radeon_vm *vm);
2713int radeon_vm_bo_update(struct radeon_device *rdev,
2970int radeon_vm_bo_update(struct radeon_device *rdev,
2714 struct radeon_vm *vm,
2715 struct radeon_bo *bo,
2971 struct radeon_bo_va *bo_va,
2716 struct ttm_mem_reg *mem);
2717void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2718 struct radeon_bo *bo);
2719struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2720 struct radeon_bo *bo);
2721struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2722 struct radeon_vm *vm,
2723 struct radeon_bo *bo);
2724int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2725 struct radeon_bo_va *bo_va,
2726 uint64_t offset,
2727 uint32_t flags);
2972 struct ttm_mem_reg *mem);
2973void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2974 struct radeon_bo *bo);
2975struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2976 struct radeon_bo *bo);
2977struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2978 struct radeon_vm *vm,
2979 struct radeon_bo *bo);
2980int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2981 struct radeon_bo_va *bo_va,
2982 uint64_t offset,
2983 uint32_t flags);
2728int radeon_vm_bo_rmv(struct radeon_device *rdev,
2729 struct radeon_bo_va *bo_va);
2984void radeon_vm_bo_rmv(struct radeon_device *rdev,
2985 struct radeon_bo_va *bo_va);
2730
2731/* audio */
2732void r600_audio_update_hdmi(struct work_struct *work);
2733struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2734struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2986
2987/* audio */
2988void r600_audio_update_hdmi(struct work_struct *work);
2989struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2990struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2991void r600_audio_enable(struct radeon_device *rdev,
2992 struct r600_audio_pin *pin,
2993 u8 enable_mask);
2994void dce6_audio_enable(struct radeon_device *rdev,
2995 struct r600_audio_pin *pin,
2996 u8 enable_mask);
2735
2736/*
2737 * R600 vram scratch functions
2738 */
2739int r600_vram_scratch_init(struct radeon_device *rdev);
2740void r600_vram_scratch_fini(struct radeon_device *rdev);
2741
2742/*

--- 70 unchanged lines hidden --- 		2997
2998/*
2999 * R600 vram scratch functions
3000 */
3001int r600_vram_scratch_init(struct radeon_device *rdev);
3002void r600_vram_scratch_fini(struct radeon_device *rdev);
3003
3004/*

--- 70 unchanged lines hidden ---